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Hardware-Efficient Interpolation-Based QR Decomposition and Lattice Reduction Processor for MIMO-OFDM Receivers

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Abstract

This paper presents the design and implementation of a joint interpolation-based QR decomposition and lattice reduction processor for the MIMO detection in 4 × 4 multiple-input multiple-output (MIMO) orthogonal frequency division multiplexing (OFDM) systems. The proposed algorithm considers the coherence bandwidth in the OFDM spectrum to reduce the computational complexity of the QR decomposition and lattice reduction. This study also proposes a MIMO preprocessing architecture and a time scheduling algorithm for allocating the tasks of the processing elements. The hardware analysis results show that the proposed design method yields the smallest area and processing time (AT) product compared to the baseline architectures under most channel environments. The proposed processor was designed and implemented in TSMC 90nm 1P9M CMOS technology. The proposed processor achieves at most 6.592 M matrix/s with 135.14 MHz clock speed and 220.68 K gates.

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Authors and Affiliations

  1. Department of Electrical Engineering, National Tsing Hua University, Taiwan, 30013, Republic of China

    Wen-Yu Chen, Chun-Fu Liao & Yuan-Hao Huang

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  1. Wen-Yu Chen
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  2. Chun-Fu Liao
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  3. Yuan-Hao Huang
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Correspondence to Yuan-Hao Huang.

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Chen, WY., Liao, CF. & Huang, YH. Hardware-Efficient Interpolation-Based QR Decomposition and Lattice Reduction Processor for MIMO-OFDM Receivers. J Sign Process Syst 88, 411–423 (2017). https://doi.org/10.1007/s11265-016-1180-z

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  • DOI: https://doi.org/10.1007/s11265-016-1180-z

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