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An Efficient VLSI Architecture for Computation of Discrete Fractional Fourier Transform

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Abstract

Since decades, the fractional Fourier transform (FrFT) has attracted researchers from various domains such as signal and image processing applications. These applications have been essentially demanding the requirement of low computational complexity of FrFT. In this paper, FrFT is simplified to reduce the complexity, and further an efficient CORDIC-based architecture for computing discrete fractional Fourier transform (DFrFT) is proposed which brings down the computational complexity and hardware requirements and provides the flexibility to change the user defined fractional angles to compute DFrFT on-the-fly. Architectural design and working method of proposed architecture along with its constituent blocks are discussed. The hardware complexity and throughput of the proposed architecture are illustrated as well. Finally, the architecture of DFrFT of the order sixteen is implemented using Verilog HDL and synthesized targeting an FPGA device ”XLV5LX110T”. The hardware simulation is performed for functional verification, which is compared with the MATLAB simulation results. Further, the physical implementation result of the proposed design shows that the design can be operated at a maximum frequency of 154 MHz with the latency of 63-clock cycles.

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Authors and Affiliations

  1. Department of Electrical Engineering, Indian Institute of Technology Patna, Bihta, Patna, 801103, India

    Kailash Chandra Ray

  2. Qualcomm India Pvt Ltd., Bangalore, 560 066, India

    M. V. N. V. Prasad

  3. Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur, 721301, India

    Anindya Sundar Dhar

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  1. Kailash Chandra Ray
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  2. M. V. N. V. Prasad
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  3. Anindya Sundar Dhar
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Correspondence to Kailash Chandra Ray.

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Ray, K.C., Prasad, M.V.N.V. & Dhar, A. An Efficient VLSI Architecture for Computation of Discrete Fractional Fourier Transform. J Sign Process Syst 90, 1569–1580 (2018). https://doi.org/10.1007/s11265-017-1281-3

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  • DOI: https://doi.org/10.1007/s11265-017-1281-3

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