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Low Power AES Using 8-Bit and 32-Bit Datapath Optimization for Small Internet-of-Things (IoT)

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Abstract

This paper proposes a low-power advanced encryption standard (AES) that can be utilized in smaller applications such as small-scale internet- of-things (IoT) devices. The proposed AES uses 8-bit and 32-bit datapaths to satisfy low power consumption and small area requirements. We use the 32-bit datapath in MixColumns only; the 8-bit datapath was used in other blocks such as SubBytes, Byte Permutation, AddRoundKey, and KeyExpansion. In addition, we propose optimized SubBytes and MixColumns to achieve low power consumption within a small area. To optimize SubBytes, we simplify the algorithm block-by-block to decrease the area. For the MixColumns, we present a 32-bit datapath that uses the proposed 0 × 02 and 0 × 03 multiplier. The AES that we have presented in this study, is implemented through Verilog-HDL and synthesized using the Samsung 65 nm standard cell library. The proposed AES shows 5400 2-input NAND gate equivalences and a power consumption of 10.01 μW (@ 0.9 V) at 10 MHz.

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Acknowledgments

This research was supported by the Ministry of Science and ICT (MSIT), Korea, under the Information Technology Research Center (ITRC) support program (IITP-2019-2016-0-00309) supervised by the Institute for Information & communications Technology Planning & Evaluation (IITP) and the National Research Foundation of Korea by the Korea government (NRF-2017R1A2A2A05001046).

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  1. School of Electronics and Computer Engineering, Ajou University, San 5, Wonchun-Dong, Yeongtong-Gu, Suwon, 443-779, South Korea

    Ho Keun Kim & Myung Hoon Sunwoo

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  1. Ho Keun Kim
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  2. Myung Hoon Sunwoo
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Correspondence to Myung Hoon Sunwoo.

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Kim, H.K., Sunwoo, M.H. Low Power AES Using 8-Bit and 32-Bit Datapath Optimization for Small Internet-of-Things (IoT). J Sign Process Syst 91, 1283–1289 (2019). https://doi.org/10.1007/s11265-019-01471-8

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  • DOI: https://doi.org/10.1007/s11265-019-01471-8

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