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The Implementation of an Amplitude-Locked Loop for Digital Communication Chip Design

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Abstract

The purpose of a communication system is to transmit an information-bearing message signal through a channel that separates a transmitter from a receiver. The modulated carrier is often induced and interfered with by various noise sources. The co-channel separation system is a demodulation process function that operates at the same carrier modulation system. Here, we adopted the field-programmable gate array (FPGA) design platform configuration to develop, implement and achieve co-channel separation for an amplitude-locked loop demodulation chip-design digital system with additive white Gaussian noise interference. In this paper, the compact reconfigurable I/O built-in FPGA chip system is integrated and applied to obtain the cross-field relevant integration function for communication and chip-design system via programming in a graphical language. Additionally, the FPGA chip-design system runs all of the program code in hardware and provides high reliability and determinism. This cross-field ideal is adopted to save time and reduce complexity in the design development of a custom circuitry system. The FPGA chip-design system described in this paper is also used to achieve a digital communication chip prototype design model, followed by presentation of the steps necessary for building and program verification. The communication and chip-design concept may provide very useful physical applications for the industry.

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Authors and Affiliations

  1. Institute of Electronic Engineering, National Kaohsiung University of Applied Sciences, Kaohsiung, Taiwan

    Gwo-Jia Jong, Yin-Chih Chen & Chen-Shen Huang

  2. Department of Computer Science and Information Engineering, Cheng-Shiu University, Kaohsiung, Taiwan

    Gwo-Jeng Yu

  3. Department of Computer Science and Information Engineering, National Cheng Kung University, Tainan, Taiwan

    Gwo-Jiun Horng

Authors
  1. Gwo-Jia Jong
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  2. Yin-Chih Chen
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  3. Chen-Shen Huang
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  4. Gwo-Jeng Yu
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  5. Gwo-Jiun Horng
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Correspondence to Gwo-Jiun Horng.

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Jong, GJ., Chen, YC., Huang, CS. et al. The Implementation of an Amplitude-Locked Loop for Digital Communication Chip Design. Wireless Pers Commun 72, 2773–2801 (2013). https://doi.org/10.1007/s11277-013-1180-2

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  • DOI: https://doi.org/10.1007/s11277-013-1180-2

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