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An Innovative Design: MOS Based Full-Wave Centre-Tapped Rectifier

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Abstract

A novel, more competent, low leakage and comparatively high speed full-wave centre-tapped rectifier is introduced with minimum distortion. Proficient and exploratory combinations of PMOS–PMOS or NMOS–NMOS logic are utilized to design full-wave centre-tapped rectifier. The scrupulous PMOS–PMOS logic with augmented stacked NMOS transistor is communal form of two PMOS and one NMOS transistor. The main motive of manipulating these circuits is to maintain the substrate biasing during circuit operation. The substrate biasing refers the exploitation in which substrate and drain/source terminal of a transistor is kept in reverse biasing mode. Due to utilization of modified MOS structure after replacing of diode, efficiency of full-wave centre-tapped rectifier is increased up to 20 % with compare to p-n junction diode based full wave centre-tapped rectifier and leakage power dissipation is reduced up to 57 %. The proposed circuit is designed to utilize the body effect properly to reduce the total leakage power of the circuit. The novelty of proposed circuit is the uniqueness of combination of MOS. Due to this; the proposed circuit has impressive resultant parameter with compare to other circuits and previous results. Proposed MOS based full-wave centre-tapped rectifier is optimized at 45 nm CMOS technology and cadence simulation experimental implementations of the leakage power and efficiency demonstrate better consistency through the proposed circuit.

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Acknowledgments

This exertion was supported by ITM University Gwalior in collaboration with Cadence System Design, Bangalore.

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Authors and Affiliations

  1. ITM University, Gwalior, MP, India

    Prateek Jain & Shyam Akashe

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  1. Prateek Jain
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  2. Shyam Akashe
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Correspondence to Prateek Jain.

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Jain, P., Akashe, S. An Innovative Design: MOS Based Full-Wave Centre-Tapped Rectifier. Wireless Pers Commun 90, 1673–1693 (2016). https://doi.org/10.1007/s11277-016-3417-3

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