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High Throughput AES Algorithm Using Parallel Subbytes and MixColumn

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Abstract

Data Security and speed is very important in many on line transaction applications. It is necessary to provide security to all the on line transaction which is done on wireless medium. Cryptography is a technique used to give protection to all the confidential data. In this paper an efficient AES cryptographic algorithm is proposed. To achieve high speed in AES algorithm an eight stage Parallel accessing technique is used in SubByte transformation S-box and an eight stage parallel computation is applied in MixColumn transformation round. The results show that AES architecture with eight stage parallelism introduced in SubByte transformation and MixColumn transformation achieves high throughput than the other architectures. In S-box eight stage parallelism gives delay of 1.013 ns and in MixColumn it gives 0.835 ns delay. Parallel processing is used AES algorithm is used to increase the throughput with the trade off of increase in area. Using the proposed architecture 58.764 Gbps throughput is achieved with the expense of 6568 slices usage when implemented on virtex5 architecture which is recorded as a higher throughput than other architectures in the literature.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Karunya University, Coimbatore, India

    S. Sridevi Sathya Priya, N. M. Sivamangai & V. Rejula

  2. Department of Electronics and Telecommunication Engineering, Karpagam College of Engineering, Coimbatore, India

    P. KarthigaiKumar

Authors
  1. S. Sridevi Sathya Priya
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  2. P. KarthigaiKumar
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  3. N. M. Sivamangai
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  4. V. Rejula
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Correspondence to S. Sridevi Sathya Priya.

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Sridevi Sathya Priya, S., KarthigaiKumar, P., Sivamangai, N.M. et al. High Throughput AES Algorithm Using Parallel Subbytes and MixColumn. Wireless Pers Commun 95, 1433–1449 (2017). https://doi.org/10.1007/s11277-016-3858-8

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  • DOI: https://doi.org/10.1007/s11277-016-3858-8

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