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Low Power Consuming 1 KB (32 × 32) Memory Array Using Compact 7T SRAM Cell

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Abstract

Rapid increase in technology is showing a great perception in assessing the complexity of design that can be integrated on a single chip dramatically. Minimum feature sizes, low power consumption, minimum cost and high performance have become the key characteristics of any electronic component. All these factors have plunged the designers into the sub micron space which brings the leakage parameters into forefront. Many electronic components especially digital designs are designed for the storage of data, highlighting the use of memory. So this paper is dedicated to the storage of data by designing 1 KB memory using SRAM. The cell used in implementing the array structure is 7T SRAM with the minimum leakage current 20.16 pA and average delay of 21 ns. This has been done in the form of an array which is a two dimensional structure of basic unit cell SRAM. The array formed in this paper is a squared array of 32 × 32. The other supporting devices in executing this array are address decoder, precharge circuit, write driver circuit and sense amplifiers. The verification of working of 1 KB SRAM array has been done in cadence virtuoso tool in 45 nm technology.

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Acknowledgements

This work has been supported by ITM University Gwalior in collaboration with Cadence virtuoso Design System, Bangalore India.

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  1. Department of Electronics and Communication Engineering, ITM University, Gwalior, MP, India

    Shalini Singh & Shyam Akashe

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  1. Shalini Singh
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  2. Shyam Akashe
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Correspondence to Shalini Singh.

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Singh, S., Akashe, S. Low Power Consuming 1 KB (32 × 32) Memory Array Using Compact 7T SRAM Cell. Wireless Pers Commun 96, 1099–1109 (2017). https://doi.org/10.1007/s11277-017-4226-z

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