Abstract
The research article presents the design of different components of FM receiver. The design approach is based on digital components rather than analog components such as phase detector, loop filter and voltage controlled oscillator. The signal is presented using digital words instead of analog voltages. In digital FM receiver, PLL is the main part to capture and lock the signals at different frequency and phase. The main purpose of PLL is to maintain the coherence between the modulated signal frequency (fi) and the respective frequency (fo), with the concept of phase comparison. PLL permits to track the frequency changes of applied input signals, as it is locked once. There is a use of 8 bit analog to digital conversion circuit, which is accepting frequency modulated signal as a series of digital numerical values. The same signals are demodulated by the receiver on every clock cycle. The paper proposed the design and FPGA implementation of digital PLL and programmable all FM receiver. The design is developed in Xilinx 14.2 ISE software and simulated in Modelsim 10.1b software with the help of VHDL programming language and the targeted onVirtex-5 FPGA.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Rylyakov, A. V., Tierno, J. A., Plouchart, J.-O., Turker, D. Z., Ainspan, H. A., & Friedman, D. (2008). A modular all-digital PLL architecture enabling both 1-to-2 GHz operation in 65 nm CMOS. In IEEE International Solid-State Circuits Conference, IEEE Xplorer, pp. 516–632.
Fahim, A. M. (2005). Clock generators for SOC processors, Ch–2 (pp. 3–24). Dordrecht: Kluwer Academic Publisher.
Huang, C.-H., Chen, Y.-C., & Jong, G.-J. (2011). The FPGA implementation of amplitude-locked loop system for co-channel communication chip design. In CSEE, pp. 458–461. Springer, Berlin.
Wang, C.-C., Sung, G.-N., Huang, J.-M., & Lin, L.-P. (2007). An 80 MHz PLL with 72.7 ps peak-to-peak jitter. Microelectronics Journal, 38, 716–721.
Stephens, D. R. (2002). Phase-locked loops for wireless communication, digital, analog and optical implementations, Ch-1 (pp. 11–58). Dordrecht: Kluwer Academic Publisher.
Hatai, I., & Chakrabarti, I. (2011). A new high-performance digital FM modulator and demodulator for software-defined radio and its FPGA implementation. International Journal of Reconfigurable Computing. doi:10.1155/2011/342532.
Hatai, I., & Chakrabarti, I. (2009). FPGA implementation of a digital FM model. In International conference on information and multimedia technology, IEEE Xplorer, pp. 475–479.
Hatai, I., & Chakrabarti, I. (2009). FPGA implementation of a digital FM modem for SDR architecture. In International conference on computers and devices for communication, IEEE Xplorer, pp. 1–4.
Segundo, J., Quintanilla, L., Arias, J., Enriques, L., Hernandez, J. M., & Vicente, J. (2009). A PLL-based synthesizer for tuneable digital clock generation in a continuous-time ∑∆ A/D converter. Integration the VLSI Journal, 42, 24–33.
Tierno, J. A., Rylyakov, A. V., & Friedman, D. J. (2008). A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI. IEEE Journal of Solid State Circuits, 43, 42–51.
Pablo, J., Brito, M., & Bampi, S. (2008). Design of a digital FM demodulator based on a 2nd-order all-digital phase-locked loop. Analog Integrated Circuits and Signal Processing, 57(1–2), 97–105.
Li, J., Luo, Y., & Tian, M. (2012). FM stereo receiver based on software-defined radio. International Journal of Digital Content Technology and its Applications, 6, 75–81.
Burbidge, M. J., & Tijou, J. (2007). Towards generic charge-pump phase-locked loop, jitter estimation techniques using indirect on chip methods. Integration the VLSI Journal, 40, 133–148.
Burnett, N. (2005). Thesis, FM radio receiver with digital demodulator. California Polytechnic State University, San Luis Obispo, pp. 1–50.
Rahmatullah, N. (2005). Research article on “Design of all digital FM receiver circuit (pp. 1–26). Bandung: Institut Teknologi Bandung.
Kumar, P. (2011). Digital phase locked loops. IETE Journal of Education, 52, 5–10.
Zikari, P., Sciagura, E., Perri, S., & Corsonello, P. (2008). A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals. Microprocessor and Microsystems, 32, 437–446.
Nonis, R., Grollitsch, W., Santa, T., Cherniak, D., & DaDalt, N. (2013). digPLL-Lite: A low-complexity, low-jitter fractional-N digital PLL architecture. IEEE Journal of Solid State Circuits, 48, 3134–3145.
Staszewski, R. B., Wallberg, J. L., Rezeq, S., Hung, C.-M., Eliezer, O. E., Vemulapalli, S. K., et al. (2005). All-digital PLL and transmitter for mobile phones. IEEE Journal of Solid State Circuits, 40, 2469–2482.
Moorthi, S., Meganathan, D., Shankar, M., Sridhar, R., & Raja Paul Perinbam, J. (2011). A low-jitter phase-locked loop architecture for clock generation in analog to digital converters. In IEEE Xplorer, pp. 81–84.
Author information
Authors and Affiliations
Corresponding author
Ethics declarations
Conflict of interest
The authors declare that there is no conflict of interests regarding the publication of this paper.
Rights and permissions
About this article
Cite this article
Kumar, A., Verma, G. & Gupta, M.K. FM Receiver Design Using Programmable PLL. Wireless Pers Commun 97, 773–787 (2017). https://doi.org/10.1007/s11277-017-4536-1
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11277-017-4536-1