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Energy-Aware and Reliability-Aware Mapping for NoC-Based Architectures

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Abstract

Extensive research has been conducted on task scheduling and mapping on a multi-processor system on chip. The mapping strategy on a network on chip (NoC) has a huge effect on the communication energy and performance. This paper proposes an efficient core mapping for NoC-based architectures. Which focus on energy- aware and reliability-aware mapping issues for NoC-based architectures and considers new applications with insignificant inter-processor communication overhead to be added to the system. This methodology was assessed by applying it to various benchmark applications. Simulation results reveal that the proposed mapping algorithm greatly improves the reliability of the system and reduce the communication energy.

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Acknowledgements

The authors thanks the Department of Electronics and Information Technology, Ministry of Communication & IT, Government of India and Media Lab Asia, to fund this work under Visvesvaraya PhD scheme.

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Authors and Affiliations

  1. National Institute of Technology Goa, Farmagudi, India

    Naresh Kumar Reddy Beechu, Vasantha Moodabettu Harishchandra & Nithin Kumar Yernad Balachandra

Authors
  1. Naresh Kumar Reddy Beechu
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  2. Vasantha Moodabettu Harishchandra
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  3. Nithin Kumar Yernad Balachandra
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Correspondence to Naresh Kumar Reddy Beechu.

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Beechu, N., Moodabettu Harishchandra, V. & Yernad Balachandra, N. Energy-Aware and Reliability-Aware Mapping for NoC-Based Architectures. Wireless Pers Commun 100, 213–225 (2018). https://doi.org/10.1007/s11277-017-5061-y

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  • DOI: https://doi.org/10.1007/s11277-017-5061-y

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