Abstract
For field programmable gate arrays (FPGAs) to retain their semiconductor market and to be competitive as a choice for portable applications, the FPGA industry must adopt new techniques for dynamic and static power reduction. In this paper, a new scheme called ‘self clock-gating’ is introduced to reduce the dynamic power of basic logic elements. Circuits are designed using 16 nm Berkeley’s Predictive technology model and tanner EDA tool is used for simulation. When we consider the average power, proposed architecture consumes 14% lesser than standard architecture. However, proposed architecture consumes only 6% of static power as that of standard architecture. If we consider the energy (power delay product), with the leakage reduction technique, the power delay product is 0.164 femto joules for the proposed architecture but in standard architecture, it is 0.200 femto joules.
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Authors acknowledge the immense help received from the scholars whose articles are cited and included in references of this manuscript. The authors are also grateful to authors/editors/publishers of all those articles, journals and books from where the literature for this article has been reviewed and discussed.
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Udaiyakumar, R., Joseph, S., Sundararajan, T.V.P. et al. Self Clock-Gating Scheme for Low Power Basic Logic Element Architecture. Wireless Pers Commun 102, 3477–3488 (2018). https://doi.org/10.1007/s11277-018-5385-2
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DOI: https://doi.org/10.1007/s11277-018-5385-2