Abstract
This paper provides a significant approach for designing the more accurate power estimation and validation models over the existing power estimation models given in the literature. It is well established that one of the existing power estimation models is not able to accurately estimate the power of the designs incorporated with low power techniques like clock enable. In this paper, an improvement over the existing power estimation model has been suggested termed as FPEV_Tool. This tool is accurately estimating the power of both types of digital circuits i.e. designs with clock enable and without clock enable specifically, with an average error of approximately 3% and peak error of 17%, respectively. The accuracy of the proposed tool is validated using Xpower Analyzer available for power analysis in Xilinx ISE and existing model given in the literature by Deng et al. This tool helps researchers to validate and compare their results with the results of existing models and commercial tools available in the market. This tool also provides a new move toward the power estimation and validation to the researchers those are working in the field of low power digital circuit design.
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The Power Estimation Model and Power Estimation Tool refers to the same meaning throughout the paper.
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Verma, G., Khare, V. & Kumar, M. More Precise FPGA Power Estimation and Validation Tool (FPEV_Tool) for Low Power Applications. Wireless Pers Commun 106, 2237–2246 (2019). https://doi.org/10.1007/s11277-018-5938-4
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DOI: https://doi.org/10.1007/s11277-018-5938-4