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LDML: A Proposal to Reduce Leakage Power in DML Circuits

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Abstract

This paper puts forward a proposal to reduce leakage power in dual mode logic (DML) circuits by adapting LECTOR (LEakage Control TransistOR) technique and the circuits so obtained are referred to as L-DML circuits. The concept is elucidated through footed Type A and Type B DML based gates which are called LDML-TA and LDML-TB. The leakage power for two and four input NAND and NOR gates implemented through DML and LDML circuits is measured in static and dynamic mode through simulative investigations at 90 nm and 45 nm nodes using the Symica DE tool. The performance of the proposal is investigated using standard and high threshold transistor variants in LECTOR technique. The dependence of leakage power on temperature is also studied for both DML and LDML circuits. It is observed that the leakage power of the circuits exhibits an upward trend with lowering of technology node and increase in temperature irrespective of the mode of operation. In static mode, the maximum power saving for LDML-TA is 58.9% at 27 °C whereas the corresponding saving in LDML-TB is 66.6% for 2-input design. Similarly, the LDML-TA and LDML-TB show power saving of (28.5%, 58.9%) and (32.5%, 66.6%) in (pre-charge, evaluate) states respectively in dynamic mode.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, 110042, India

    Neetika Yadav, Neeta Pandey & Deva Nand

  2. Department of Electronics and Communication Engineering, Amity School of Engineering and Technology (Affiliated to GGSIPU), Sector 125, Noida, 201303, India

    Neetika Yadav

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  1. Neetika Yadav
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Correspondence to Deva Nand.

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Yadav, N., Pandey, N. & Nand, D. LDML: A Proposal to Reduce Leakage Power in DML Circuits. Wireless Pers Commun 129, 1009–1024 (2023). https://doi.org/10.1007/s11277-023-10170-4

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