Skip to main content
SpringerLink
Log in

Design and Verification of High-Speed VLSI Physical Design

  • Published:
Journal of Computer Science and Technology Aims and scope Submit manuscript

Abstract

With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement, interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis, parasitic extraction, and clock signal distribution are briefly reviewed.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. International Technology Roadmap for Semiconductors (ITRS). 2003.

  2. Bakoglu H B. Circuits, Interconnections and Packaging for VLSI. MA: Addision-Wesley, 1990.

    Google Scholar 

  3. Sahookar K, Mazumder P. VLSI cell placement techniques. ACM Computing Surveys, June 1991, 23(2): 143–220.

    Google Scholar 

  4. Sherwani N. Algorithms for VLSI Physical Design Automation. second edition, Kluwer Academic Publishers, 1995.

  5. Kirkpatrick S, Gelatt C D, Vecchi M P. Optimization by simulated annealing. Science, May, 1983, pp.671–680.

  6. Lam J, Delosme J. Logic minimization using simulated annealing. In Proc. the IEEE Int. Conf. Computer-Aided Design, 1986, pp.378.

  7. Otten R, Vanginnekin L. Floorplan design using simulated annealing. In Proc. the IEEE Int. Conf. Computer-Aided Design, 1984, pp.96–98.

  8. Sechen C, Sangiovanni-Vincentelli A. The TimberWolf placement and routing package. IEEE Journal of Solid-State Circuits, Apr. 1985, 20: 510–522.

    Google Scholar 

  9. Sechen C, Sangiovanni-Vincentelli A. TimberWolf3.2: A new standard cell placement and global routing package. In Proc. the 23rd Design Automation Conference, 1986, pp.432–439.

  10. Sham C-W, Young E F Y. Routability-driven floorplanner with buffer block planning. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, April 2003, 22: 470–480.

    Google Scholar 

  11. Kim J-G, Kim Y-D. A linear programming-based algorithm for floorplanning in VLSI design. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, May 2003, 22: 1550–1556.

    Google Scholar 

  12. Murata H, Fujiyoshi K, Kajitani Y. VLSI module placement based on rectangle-packing by the sequence-pair. IEEE Trans. Computer-Aided Design, Dec. 1996, 15: 1518–1524.

    Google Scholar 

  13. Alupoaei S, Katkoori S. Net-based force-directed macrocell placement for wirelength optimization. IEEE Trans. Very Large Scale Integration (VLSI) Systems, Dec. 2002, 10: 824–835.

    Google Scholar 

  14. Choi W, Bazargan K. Hierarchical global floorplacement using simulated annealing and network flow area migration. Design, Automation and Test in Europe Conference and Exhibition, 2003, pp.1104–1105.

  15. Kleinhans J M, Sigl G, Johannes F M, Antreich K J. GORDIAN: VLSI placement by quadratic programming and slicing optimization. IEEE/ACM Int. Conf. Computer Aided Design, March 1991, 10: 356–365.

    Google Scholar 

  16. Quinn N R. The placement problem as viewed from the physics of classical mechanics. In Proc. 12th Design Automa-tion Conf., June 1975, pp.173–178.

  17. Eisenmann H, Johannes F M. Generic global placement and floorplanning. In Proc. Design Automation Conf., June 1998, pp.269–274.

  18. Goplen B, Sapatnekar S. Efficient thermal placement of standard cells in 3D ICs using a force directed approach Goplen. In Proc. Int. Conf. Computer Aided Design, Nov. 9–13, 2003, pp.86–89.

  19. Lee J. Thermal placement algorithm based on heat conduction analogy. IEEE Trans. Components and Packaging Technologies, June 2003, 26(2): 473–482.

    Google Scholar 

  20. Viswanathan N, Chu C. FastPlace: Efficient analytical placement using cell spreading, iterative local refinement and a hybrid net model. In Proc. Int. Symp. Physical Design, 2004, pp.26–33.

  21. Breuer M A. A class of min-cut placement algorithms. In Proc. Design Automation Conf, 1977, pp.284–290.

  22. Dunlop A E, Kernighan B W. A procedure for placement of standard-cell VLSI circuits. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, January 1985, CAD-4(1): 92–98.

    Google Scholar 

  23. Kernighan B W, Lin S. An efficient heuristic procedure for partitioning graphs. Bell Syst. Tech. J. 1970, 49(2): 291–308.

    Google Scholar 

  24. Fiduccia C M, Mattheyses R M. A linear-time heuristic for improving network partitions. In Proc. the 19th Design Automation Conf., 1982, pp.175–181.

  25. Alpert C J, Huang J-H, Kahng A B. Multilevel circuit partitioning. In Proc. Design Automation Conf., 1997, pp.530–533.

  26. Karypis G, Aggarwal R, Kumar V, Shekhar S. A Multilevel hypergraph partitioning: Applications in VLSI design. In Proc. Design Automation Conf., 1997, pp.526–529.

  27. Caldwell A E, Kahng A B, Markov I L. Can mrecursive bisection alone produce routable placements? In Proc. Design Automation Conf., 2000, pp.526–529.

  28. Yildiz M C, Madden P H. Improved cut sequences for partitioning based placement. In Proc. Design Automation Conf., 2001, pp.776–779.

  29. Agnihotri A et al. Fractional cut: Improved recursive bisection placement. In Proc. Int. Conf. Computer Aided Design, 2003, pp.307–310.

  30. Caldwell A E, Kahng A B, Markov I L. Improved algorithms for hypergraph bipartitioning. In Proc. Asia South Pacific Design Automation Conf., 2000, pp.661–666.

  31. Wang M, Yang X, Sarrafzadeh M. Dragon2000: Standard-cell placement tool for large industry circuits. In Proc. Int. Conf. Computer Aided Design, November 2000, pp.260–263.

  32. Brandt A. Multi-level adaptive technique (MLAT) for fast numerical solution to boundary value problems. In Proc. 3rd Int. Conf. Numerical Methods in Fluid Mechanics, Vol. 1, Cabannes, Temam R (eds.), Lecture Notes in Physics 18, Springer, Berlin, pp.82–89.

  33. Brandt A. Multi-level adaptive solutions to boundary value problems. Math. Comput., 31: 333–390.

  34. Briggs W L. A Multigrid Tutorial. SIAM Books, Philadelphia, 1987.

    Google Scholar 

  35. Trottenberg U, Osterlee C W, Schler A. Multigrid.

  36. Hong X, Yu H, Qiao C, Cai Y. CASH: A novel quadratic placement algorithm for very large standard cell layout design based on clustering. In Proc. 5th Int. Conf. Solid-State and Integrated Circuit Technology, 1998, pp.496–501.

  37. Chan T F, Cong J, Kong T, Shinnerl J R. Multilevel optimization for large-scale circuit placement. In Proc. Int. Conf. Computer Aided Design, Nov., 2000, pp.171–176.

  38. Chang T F, Cong J, Kong T, Shinnel J R, Sze K. An enhanced multilevel algorithm for circuit placement. In Proc. Int. Conf. Computer Aided Design, Nov., 2003, pp.299–306.

  39. Chen H, Cheng C-K, Chou N-C, Kahng A B. An algebraic multigrid solver for analytical placement with layout based clustering. In Proc. Design Automation Conf., June 2003, pp.794–799.

  40. Cong J, Yuan X. Multilevel global placement with retiming. In Proc. Design Automation Conf., pp.208–213.

  41. Chang C C, Cong J, Pan Z, Yuan X. Multilevel global placement with congestion control. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, April 2003, 22: 395–409.

    Google Scholar 

  42. Lee H-C, Chang Y-W, Hsu J-M, Yang H H. Multilevel floorplanning/placement for large-scale modules using b*-trees. In Proc. Design Automation Conference, June 2003, pp.812–817.

  43. Yang X, Choi B-K, Sarrafzadeh M. Routability driven white space allocation for fixed-die standard-cell placement. ACM Int. Symp. Physical Design, April 2002, pp.42–47.

  44. Cong J, Kong T, Pan D Z. Buffer block planning for interconnectdriven floorplanning. In Proc. Int. Conf. Computer-Aided Design, 1999, pp.358–363.

  45. Alpert C J, Hu J, Sapatnekar S, Villarubia P G. A practical methodology for early buffer and wire resource allocation. In Proc. Design Automation Conf., 2001, pp.189–194.

  46. Nakatake S, Sakanushi K, Kajitani Y, Kawatika M. The channeled BSG: A universal floorplanner for simultaneous place/route with IC applications. In Proc. IEEE Int. Conf. Computer-Aided Design, 1998, pp.418–425.

  47. Chen H, Zhou H, Young F Y, Wong D F, Yang Y, Sherwani N. Integrated floorplanning and interconnect planning. In Proc. IEEE Int. Conf. Computer-Aided Design, 1999, pp.354–357.

  48. Sylvester D, Keutzer K. Impact of small process geometries on microarchitectures in systems on a chip. In Proc. IEEE, 2001, 89(4): 467–489.

    Google Scholar 

  49. Adler V, Friedman E G. Repeater design to reduce delay and power in resistive interconnect. IEEE Trans. Circuits Syst. I, May 1998, 45: 607–616.

    Google Scholar 

  50. Bakoglu H B, Meindl J D. Optimal interconnection circuits for VLSI. IEEE Trans. Electron Devices, May 1985, ED-32: 903–909.

    Google Scholar 

  51. Alpert C, Devgan A. Wire segmenting for improved buffer insertion. In Proc. ACM/IEEE DAC, 1997, pp.588–593.

  52. Chu C, Wong D F. Closed form solution to simultaneous buffer insertion/sizing and wire sizing. ACM Trans. Design Automation of Electronic Systems, July 2001, 6(3): 343–371.

    Google Scholar 

  53. Cong J, Leung K. Optimal wire sizing under the distributed Elmore delay model. In Proc. IEEE ICCAD, 1993, pp.634–639.

  54. Dhar S, Franklin M A. Optimum buffer circuits for driving long uniform lines. IEEE J. Solid-State Circuits, Jan. 1991, 26: 32–40.

    Google Scholar 

  55. Nekili M, Savaria Y. Parallel regeneration of interconnections in VLSI & ULSI circuits. In Proc. IEEE Int. Symp. Circuits and Systems, May 1993.

  56. Cong J, He L, Koh C-K, Madden P H. Performance optimization of VLSI interconnect layout. Integration VLSI J., 1996, 21: 1–94.

    Google Scholar 

  57. Cong J, He L, Khoo K-Y, Koh C-K, Pan D Z. Interconnect design for deep submicron ICs. In Proc. Int. Conf. Computer-Aided Design, San Jose, CA, Nov. 1997, pp.478–485.

  58. Zhou D, Preparata F P, Kang S M. Interconnection delay in very high-speed VLSI. IEEE Trans. Circuits and Systems, July 1991, 38(7).

  59. Davis J A, Meindl J D. Compact distributed RLC interconnect models—Part I: Single line transient, time delay, and overshoot expressions. IEEE Trans. Electron. Devices, 47(11): 2068–2077.

  60. Davis J A, Meindl J D. Compact distributed RLC interconnect models—Part II: Coupled line expressions, and peak crosstalk in multilevel networks. IEEE Trans. Electron. Devices, 47(11): 2078–2087.

  61. Venkatesan R, Davis J A, Meindl J D. Compact distributed RLC interconnect models—Part III: Transients in single and coupled lines with capacitive load termination. IEEE Trans. Electron. Devices, 50(4): 1081–1093.

  62. Venkatesan R, Davis J A, Meindl J D. Compact distributed RLC interconnect models—Part IV: Unified models for time delay, crosstalk, and repeater insertion. IEEE Trans. Electron. Devices, 50(4): 1094–1102.

  63. Elmore W C. The transient response of damped linear network with particular regard to wideband amplifiers. J. Appl. Phys., 1948, 19: 55–63.

    Google Scholar 

  64. Zhou D, Su S, Tsui F, Gao D S, Cong J S. A simplified synthesis of transmission lines with a tree structure. Int. J. Analog Integrated Circuits Signal Process, Jan. 1994, 5: 19–30.

    Google Scholar 

  65. Kahng A B, Muddu S. An analytical delay model for RLC interconnects. IEEE Trans. Computer-Aided Design, Dec. 1997, 16: 1507–1514.

    Google Scholar 

  66. Tutuianu B, Dartu F, Pileggi L. Explicit RC-circuit delay approximation based on the first three moments of the impulse response. IEEE/ACM Design Automation Conf., June 1996, pp.611–616.

  67. Pillage L T, Rohrer R A. Asymptotic waveform evaluation fortiming analysis. IEEE Trans. Computer-Aided Design, Apr. 1990, 9: 352–366.

    Google Scholar 

  68. Feldmann P, Freund R W. Efficient linear circuit analysis by Pad approximation via the Lanczos process. IEEE Trans. Computer-Aided Design, May 1995, 14: 639–649.

    Google Scholar 

  69. Feldmann P, Freund R W. Reduced-order modeling of large linear subcircuits via block Lanczos algorithm. In Proc. IEEE/ACM Design Automation Conf., June 1995, pp.474-479.

  70. Silveira M, Kamon M, White J. Efficient reduced-order modeling of frequency-dependent coupling inductances associated with 3-D interconnect structures. In Proc. IEEE/ACM Design Automation Conf., June 1995, pp.376–380.

  71. Boley D L. Krylov space methods on state-space control models. J. Circuits, Syst., Signal Processing, May 1994, 13(6): 733–758.

    Google Scholar 

  72. Odabasioglu A, Celik M, Pillage L T. PRIMA: Passive reduced-order interconnect macromodeling algorithm. IEEE Trans. Computer-Aided Design, Aug. 1998, 17: 645–654.

    Google Scholar 

  73. Feldmann P, Freund R W. Reduced-order modeling of large passive linear circuits by means of the SyPVL algorithm. In Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 1996, pp.280–287.

  74. Ismail Y I, Friedman E G, Neves J L. Equivalent Elmore delay for RLC trees. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Jan. 2000, 19(1): 83–97.

    Google Scholar 

  75. Cong J, Leung K S, Zhou D. Performance-driven interconnect design based on distributed RC delay model. In Proc. Design Automation Conf., June 1993, pp.606–611.

  76. Fishburn J P, Schevon C A. Shaping a distributed-RC line to minimize Elmore delay. IEEE Trans. Circuits Syst. I: Fund. Theory Applicat., Dec. 1995, 42(12): 1020–1022.

    Google Scholar 

  77. Chen C P, Chen Y P, Wong D F. Optimal wire-sizing formula under the Elmore delay model. In Proc. Design Automation Conf., June, 1996, pp.487–490.

  78. Chen C-P, Wong D F. Optimal wire sizing function with fringing capacitance consideration. In Proc. Design Automation Conf., June, 1997, pp.604–607.

  79. Fishburn J P. Shaping a VLSI wire to minimize Elmore delay. In Proc. European Design and Test Conf., Mar. 1997.

  80. Gao Y, Wong D F. Optimal shape function for a bi-directional wire under Elmore delay model. In Proc. Int. Conf. Computer Aided Design, Nov. 1997, pp.622–627.

  81. Chen C-P, Wong D F. A fast algorithm for optimal wire-sizing under Elmore delay model. In Proc. IEEE ISCAS, 1996, 4: 412–415.

    Google Scholar 

  82. Chu C, Wong D F. Greedy wire-sizing is linear time. IEEE Trans. Computer-Aided Design, Apr. 1999, 18: 398–405.

    Google Scholar 

  83. Fishburn J P. Shaping a VLSI wire to minimize Elmore delay. European Design and Design and Test Conf., 1997.

  84. Chen C-P, Zhou H, Wong D F. Optimal nonuniform wire-sizing under the Elmore delay model. IEEE Int. Conf. Computer-Aided Design, 1996, pp.192–197.

  85. Cong J, He L. Optimal wiresizing for interconnects with multiple sources. ACM Trans. Design Automation Electron. Syst., Oct. 1996, 1(4): 478–511.

    Google Scholar 

  86. Menezes N, Pullela S, Dartu F, Pillage L T. RC interconnect synthesis—A moment fitting approach. In Proc. Int. Conf. Computer-Aided Design, Nov. 1994, pp.418–425.

  87. Pileggi L. Coping with RC(L) interconnect design headaches. In Proc. Int. Conf. Computer-Aided Design, Nov. 1995, pp.246–253.

  88. Cong J, He L, Koh C-K, Pan Z. Global interconnect sizing and spacing with consideration of coupling capacitance. In Proc. Int. Conf. Computer-Aided Design, Nov. 1997, pp.628–633.

  89. Cong J, Pan Z. Wire width planning for interconnect performance optimization. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, March 2002, 21: 319–329.

    Google Scholar 

  90. Chen T-C, Pan S-R, Chang Y-W. Timing modeling and optimization under the transmission line model. IEEE Trans. Very Large Scale Integration (VLSI) Systems, Jan. 2004, 12: 28–41.

    Google Scholar 

  91. Hedenstierna N, Jeppson K O. CMOS circuit speed and buffer optimization. IEEE Trans. Computer-Aided Design, Mar., 1987, CAD-6: 270–281.

    Google Scholar 

  92. Jaeger R C. Comments on ‘An optimized output stage for MOS integrated circuits’. IEEE J. Solid-State Circuits, June, 1975, SC-10: 185–186.

    Google Scholar 

  93. Lin H C, Linholm L W. An optimized output stage for MOS integrated circuits. IEEE J. Solid-State Circuits, April, 1975, SC-10: 106–109.

    Google Scholar 

  94. van Ginneken L P P P. Buffer placement in distributed RC-tree network for minimal Elmore delay. ISCAS 1990, pp.865–868.

  95. Shi W, Li Z. An O(nlog n) time algorithm for optimal buffer insertion. DAC 2003, pp.580–585.

  96. Lillis J, Cheng C-K, Lin T. Optimal wire sizing and buffer insertion for low power and a generalized delay model. IEEE/ACM ICCAD, 1995, pp.138–143.

  97. Lillis J, Cheng C-K, Lin T Y, Ho C. New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing. Design Automation Conference Proceedings, 1996, pp.395–400.

  98. Kamoto T, Cong J. Buffered Steiner tree construction with wire sizing for interconnect layout optimization. IEEE/ACM Int. Conf. Computer-Aided Design, 1996, pp.44–49.

  99. Kang M, Dai W W-M, Dillinger T, LaPotin D. Delay bounded buffered tree construction for timing driven floorplanning. ICCAD 1997, pp.707–712.

  100. Zhou H, Wong D F, Liu I M, Aziz A. Simultaneous routing and buffer insertion with restrictions on buffer locations. IEEE Trans. CAD, 2000, 19(7): 819–824.

    Google Scholar 

  101. Chu C C N, Wong D F. A polynomial time optimal algorithm for simultaneous buffer and wire sizing. In Proc. Conf. Design Automation and Test in Europe, 1998, pp.479–485.

  102. Cong J, Koh C-K, Leung K-S. Simultaneous buffer and wire sizing for performance and power optimization. In Proc. Int. Symp. Low-Power Electronics and Design, Aug. 1996, pp.271–276.

  103. Mo Y, Chu C. Hybrid dynamic/quadratic programming algorithm for interconnect tree optimization. IEEE Trans. Computer-Aided Design, May 2001, 20(5): 680–686.

    Google Scholar 

  104. Chu C, Wong D F. A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing. IEEE Trans. Computer-Aided Design, 1999, 18(6): 787–798.

    Google Scholar 

  105. Menezes N, Baldick R, Pileggi L T. A sequential quadratic programming approach to concurrent gate and wire sizing. In Proc. IEEE Int. Conf. Computer-Aided Design, 1995, pp.144–151.

  106. Lillis J, Cheng C-K, Lin T-T. Optimal wire sizing and buffer insertion for low power and a generalized delay model. IEEE J. Solid State Circuits, Mar., 1996, 31: 437–447.

    Google Scholar 

  107. Banerjee K, Mehrotra A. A power-optimal repeater insertion methodology for global interconnects in nanometer designs. IEEE Transaction on Electron Devices, Nov., 2002, 49(11).

  108. Turgis S, Azemard N, Auvergne D. Design and selection of buffers for minimum power-delay product. In Proc. European Design and Test Conference, 1996, pp.224–228.

  109. Zhou D, Liu X. Minimization of chip size and power consumption of high-speed VLSI buffers. In Proc. Int. Symp. Physical Design, 1997, pp.186–191.

  110. Nalamalpu A, Burleson W. A practical approach to DSM repeater insertion: Satisfying delay constraints while minimizing area and power. In Proc. 14th Annu. IEEE Int. ASIC/SOC Conf., 2001, pp.152–156.

  111. Li R, Zhou D, Liu J, Zeng X. Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing. In Proc. International Conference on CAD, Nov. 2003.

  112. Pillage L T, Rohrer R A. ąAsymptotic waveform evaluation for timing analysis. IEEE Trans. CAD, Appil, 1990, 9(4): 352–366.

    Google Scholar 

  113. Zhou D, Chen N, Cai W. A fast wavelet collocation method for high-speed circuit simulation. In Proc. IEEE/ACM ICCAD, 1995, pp.115–122.

  114. Zhou D, Cai W. A fast wavelet collocation method for high-speed circuit simulation. IEEE Trans. CAS-I, 1999, pp.920–930.

  115. Zhou D, Cai W, Zhang W. An adaptive wavelet method for nonlinear circuit simulation. IEEE Trans. CAS-I, 1999, pp.931–938.

  116. Rabiei P, Pedram M. Model order reduction of large circuits using balanced truncation. In Proc. ASP-DAC, 1999, pp.237–240.

  117. Glover K. All optimal Hankel-norm approximations of linear multivariable systems and their L error bounds. Int. J. Control, 1984, 39(6): 1115–1193.

    Google Scholar 

  118. Chiprout E, Nakhla M S. Asymptotic waveform evaluation and moment matching for interconnect analysis. Kluwer Academic, Norwell, MA, 1994.

    Google Scholar 

  119. Chiprout E, Nakhla M S. Analysis of interconnect networks using complex frequency hopping (CFH). IEEE Trans. CAD Integrated Circuits and Systems, 1995, 14(2): 186–200.

    Google Scholar 

  120. Ismail Y I. Efficient model order reduction via multi-node moment matching. IEEE/ACM International Conference on Computer-Aided Design, Nov. 2002, pp.767–774.

  121. Ismail Y I. Improved model-order reduction by using spacial information in moments. IEEE Trans. Very Large Scale Integration (VLSI) Systems, Oct. 2003, 11: 900–908.

    Google Scholar 

  122. Bai Z, Slone R D, Smith W T, Qiang Y. Error bound for reduced system model by Pade approximation via the Lanczos process. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Feb. 1999, 18: 133–141.

    Google Scholar 

  123. Wittig T, Munteanu I, Schuhmann R, Weiland T. Two-step Lanczos algorithm for model order reduction. IEEE Trans. Magnetics, March 2002, 38: 673–676.

    Google Scholar 

  124. Silveira M, Kamon M, Elfadel I, White J. A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits. IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 1996, pp.288–294.

  125. Grimme E J, Sorensen D C, Van Dooren P. Model reduction of state space systems via an implicitly restarted Lanczos method. Numer. Algorithms, 1996, 12(1-2): 1–31.

    Google Scholar 

  126. Odabasioglu A, Celik M, Pileggi L. PRIMA: Passive reduced-order interconnect macromodeling algorithm, ąi. In Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1997, pp.58–65.

  127. Liu Y, Pileggi L T, Strojwas A J. Model order-reduction of RC(L) interconnect including variational analysis. Design Automation Conference, June 1999, pp.201–206.

  128. Wang J M, Chia-Chi Chu, Qingjian Yu, Kuh E S. On projection-based algorithms for model-order reduction of interconnects. IEEE Trans. Circuits and Systems I: Fundamental Theory and Applications, Nov. 2002, 49: 1563–1585.

    Google Scholar 

  129. Zhou D, Li W, Cai W, Guo N. An efficient balanced truncation realization algorithm for interconnect model order reduction. IEEE International Symposium on Circuits and Systems, May 2001, pp.383–386.

  130. Zeng X, Zhou D, Cai W. An efficient DC-gain matched balanced truncation realization for VLSI interconnect circuit order reduction. Microelectronic Engineering, January 2002, 60: 3–15.

    Google Scholar 

  131. Philips J R, Daniel L, Silveira L M. Guaranteed passive balancing transformations for model order reduction. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Aug. 2003, 22: 1027–1041.

    Google Scholar 

  132. Mei S, Amin C, Ismail Y I. Efficient model order reduction including skin effect. Design Automation Conference, June, 2003, pp.232–237.

  133. Shin Y, Sakurai T. Power distribution analysis of VLSI interconnects using model order reduction. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, June 2002, 21: 739–745.

    Google Scholar 

  134. Rewienski M, White J. A trajectory piecewise-linear approach to model order reduction and fast simulation of nonlinear circuits and micromachined devices. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Feb. 2003, 22: 155–170.

    Google Scholar 

  135. Dong N, Roychowdhury J. Piecewise polynomial nonlinear model reduction. In 40th ACM/IEEE Design Automation Conference, Anaheim, CA, June 2003, pp.484–489.

  136. Chen Y. Model order reduction for nonlinear systems [Thesis]. Massachusetts Institute of Technology, September 1999.

  137. Phillips J R. Projection frameworks for model reduction of weakly nonlinear systems. Design Automation Conference, June, 2000.

  138. Phillips J R. Automated extraction of nonlinear circuit macromodels. IEEE Custom Integrated Circuits Conference, 2000.

  139. Roychowdhury J. Reduced-order modeling of time-varying system. IEEE Trans. CAS Part II, Oct., 1999, 46(10).

  140. Feng L, Zeng X, Chiang C, Zhou D, Fang Q. Direct nonlinear order reduction with variational analysis. Design, Automation and Test in Europe Conference and Exhibition, 2004, 2: 1316–1321.

    Google Scholar 

  141. Li P, Pileggi L T. NORM: Compact model order reduction of weakly nonlinear systems. Design Automation Conference, June, 2003, pp.472–477.

  142. Phillips J, Afonso J, Oliveira A, Silveira L M. Analog macromodeling using kernel methods. IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 2003, pp.446–453.

  143. Chen T-H, Chen C C-P. Efficient large-scale power grid analysis based on preconditioned Krylov-subspace iterative methods. Design Automation Conf., June 2003, pp.559–562.

  144. Lee Y-M, Chen C C-P. Power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit method. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Nov. 2002, 21: 1343–1352.

    Google Scholar 

  145. Lee Y-M, Chen C C-P. The power grid transient simulation in linear time based on 3-D alternating-direction-implicit method. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Nov. 2003, 22: 1545–1550.

    Google Scholar 

  146. Kozhaya J N, Nassif S R, Najm F N. A multigrid-like technique for power grid analysis. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Oct. 2002, 21: 1148–1160.

    Google Scholar 

  147. Su H, Acar E, Nassif S R. Power grid reduction based on algebraic multigrid principles. Design Automation Conference, June 2003, pp.109–112.

  148. Zhu Z, Yao B, Cheng C-K. Power network analysis using an adaptive algebraic multigrid approach. Design Automation Conference, June 2003, pp.105–108.

  149. Wang K, Marek-Sadowska M. On-chip power supply network optimization using multigrid-based technique. Design Automation Conference, June 2003, pp.113–118.

  150. Qian H, Nassif S R, Sapatnekar S S. Random walks in a supply network. Design Automation Conf., June 2003, pp.93–98.

  151. Kouroussis D, Najm F N. A static pattern-independent technique for power grid voltage integrity verification. Design Automation Conf., June 2003, pp.99–104.

  152. Zhao M, Panda R V, Sapatnekar S S, Blaauw D. Hierarchical analysis of power distribution networks. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Feb. 2002, 21: 159–168.

    Google Scholar 

  153. Chen H, Neely J. Interconnect and circuit modeling techniques for full-chip power supply noise analysis. IEEE Trans. Components, Packaging and Manufacturing Technology, Part B, August 1998, 21(3): 209–215.

    Google Scholar 

  154. Kao W H, Lo C-Y, Basel M, Singh R. Parasitic extraction: Current state of the art and future trends. In Proc. the IEEE, May 2001, 89: 729–739.

    Google Scholar 

  155. Greengard L. The Rapid Evaluation of Potential Fields in Particle Systems. Cambridge, MA: MIT Press, 1987.

    Google Scholar 

  156. Kamon M, Tsuk M, White J. FastHenry: A multipole accelerated 3-D inductance extraction program. IEEE Trans. Microwave Theory Tech., Sept. 1994, 42: 1750–1758.

    Google Scholar 

  157. Nabors K, White J K. FASTCAP: A multipole-accelerated 3-D capacitance extraction program. IEEE Trans. Computer-Aided Design, Nov. 1991, 10: 1447–1459.

    Google Scholar 

  158. Shi W, Liu J, Kakani N, Yu T. A fast hierarchical algorithm for three-dimensional capacitance extraction. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, March 2002, 21: 330–336.

    Google Scholar 

  159. Beattie M W, Pileggi L T. Parasitics extraction with multipole refinement. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Feb. 2004, 23: 288–292.

    Google Scholar 

  160. Yan S, Liu J, Shi W. Improving boundary element methods for parasitic extraction. In Proc. the Asia and South Pacific Design Automation Conf., Jan. 2003, pp.261–267.

  161. Friedman E G. Clock distribution networks in synchronous digital integrated circuits. In Proc. the IEEE, May 2001, 89: 665–692.

    Google Scholar 

  162. Fishburn J P. Clock skew optimization. IEEE Trans. Comput., July 1990, 39: 945–951.

    Google Scholar 

  163. Szymanski T G, Shenoy N. Verifying clock schedules. In Proc. IEEE Int. Conf. Computer-Aided Design, Nov. 1992, pp.124–131.

  164. Deokar R B, Sapatnekar S S. A graph-theoretic approach to clock skew optimization. In Proc. the IEEE Int. Symp. Circuits and Systems, 1995, pp.407–410.

  165. Shenoy N, Brayton R K, Sangiovanni-Vincentelli A L. Graph algorithms for clock schedule optimization. Int. Conf. Computer-Aided Design, 1992, pp.132–136.

  166. Szymanski T. Computing optimal clock schedules. In Proc. Design Automation Conf., June 1992, pp.399–404.

  167. Albrecht C, Korte B, Schietke J, Vygen J. Cycle time and slack optimization for VLSI-Chips. Int. Conf. Computer Aided Design, 1999, pp.232–238.

  168. Kourtev I S, Friedman E G. Timing Optimization Through Clock Skew Scheduling. Kluwer, Boston, 2000.

    Google Scholar 

  169. Kourtev I S, Friedman E G. A quadratic programming approach to clock skew scheduling for reduced sensitivity to process parameter variations. In Proc. the IEEE Int. ASIC/SOC Conference, 1999, pp.210–215.

  170. Held S et al. Clock scheduling and clocktree construction for high performance ASICs. Int. Conf. Computer-Aided Design, Nov. 2003, pp.232–239.

  171. Huang S-H, Nieh Y-T. Clock period minimization of non-zero clock skew circuits. Int. Conf. Computer-Aided Design, Nov. 2003, pp.809–812.

  172. Leiserson C E, Saxe J B. Retiming synchronous circuitry. Algorithmica, 1991, 6: 5–35.

    Google Scholar 

  173. Chu C, Young E F Y, Tong D K Y, Dechu S. Retiming with interconnect and gate delay. Int. Conf. Computer-Aided Design, Nov. 2003, pp.221–226.

  174. Ravindran K, Kuehlmann A, Sentovich E M. Multi-domain clock skew scheduling. Int. Conf. Computer-Aided Design, Nov. 2003, pp.801–808.

  175. Velenis D, Papaefthymiou M C, Friedman E G. Reduced delay uncertainty in high performance clock distribution networks. Design, Automation and Test in Europe Conference and Exhibition, 2003, pp.68–73.

Download references

Author information

Authors and Affiliations

  1. Department of Electrical Engineering, The University of Texas at Dallas, Richardson, TX, 75083-0688, U.S.A.

    Dian Zhou & Rui-Ming Li

  2. School of Microelectronics, Fudan University, Shanghai, 200433, P.R. China

    Dian Zhou

Authors
  1. Dian Zhou
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Rui-Ming Li
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Dian Zhou.

Additional information

This research is supported by U. S. NSF CCR-0098275 and CCR-0306298.

Dian Zhou received the B.S. degree in physics and M.S. degree in electrical engineering from Fudan University, P.R. China, in 1982 and 1985, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign, in 1990. He is currently a Changjiang Honor Professor and the Dean, School of Microelectronics at Fudan University (on leave from the E.E. Department, University of Texas at Dallas). His research and teaching interests include: VLSI design, high performance VLSI circuits, telecommunication hardware and systems, mixed-signal circuits, and algorithms.

Rui-Ming Li received M.S. degree from the Department of Electrical Engineering, University of Texas at Dallas in 2001, now working toward his Ph.D. degree. He was a lecturer at the Department of Applied Mathematics, Ocean University of China before joining UTD.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Zhou, D., Li, RM. Design and Verification of High-Speed VLSI Physical Design. J Comput Sci Technol 20, 147–165 (2005). https://doi.org/10.1007/s11390-005-0147-5

Download citation

  • Received:

  • Revised:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11390-005-0147-5

Keywords

Search

Navigation