Skip to main content
SpringerLink
Log in

Parallel Error Detection for Leading Zero Anticipation

  • Short Paper
  • Published:
Journal of Computer Science and Technology Aims and scope Submit manuscript

Abstract

The algorithm and its implementation of the leading zero anticipation (LZA) are very vital for the performance of a high-speed floating-point adder in today’s state of art microprocessor design. Unfortunately, in predicting “shift amount” by a conventional LZA design, the result could be off by one position. This paper presents a novel parallel error detection algorithm for a general-case LZA. The proposed approach enables parallel execution of conventional LZA and its error detection, so that the error-indication signal can be generated earlier in the stage of normalization, thus reducing the critical path and improving overall performance. The circuit implementation of this algorithm also shows its advantages of area and power compared with other previous work.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Schmookler M S, Nowka K J. Leading zero anticipation and detection—A comparison of methods. In Proc. 15th IEEE Symposium on Computer Arithmetic, Vail, CO, USA, June 11–13, 2001, pp.7–12.

  2. Montoye R K, Hokenek E, Runyon S L. Design of the IBM RISC system/6000 floating-point execution unit. IBM Journal of Research and Development, 1990, 34(1): 59–71.

    Article  Google Scholar 

  3. Oberman S. Floating-point arithmetic unit including an efficient close data path. US Patent 6094668, AMD, 2000.

  4. Gorshtein V, Grushin A, Shevtsov S. Floating-point addition methods and apparatus. US Patent 5808926, Sun Microsystems, 1998.

  5. Peter Michael Seidel, Guy Even. Delay-optimized implementation of IEEE floating-point addition. IEEE Transactions on Computers, 2004, 53(2): 97–113.

    Article  Google Scholar 

  6. Hays W et al. A 32-bit VLSI digital signal processor. IEEE Journal of Solid State Circuits, October 1985, 20(5): 998–1004.

    Article  Google Scholar 

  7. Hokenek E, Montoye R. Leading-zero anticipator (LZA) in the IBM RISC system/6000 floating point execution unit. IBM Journal of Research and Development, 1990, 34(1): 71–77.

    Google Scholar 

  8. Suzuki H et al. Leading-zero anticipatory logic for high-speed floating point addition. IEEE Journal of Solid State Circuits, 1996, 31(8): 1157–1164.

    Article  Google Scholar 

  9. Gerwig G, Kroener M. Floating-point unit in standard cell design with 116-bit wide dataflow. In Proc. 14th IEEE Symposium on Computer Arithmetic, Adelaide, Australia, April 14–16, 1999, pp.266–273.

  10. Bruguera J, Lang T. Leading-one prediction scheme for latency improvement in single datapath floating-point adders. In Proc. International Conference on Computer Design, Austin, Texas, USA, October 5–7, 1998, pp.298–305.

  11. Bruguera J, Lang T. Leading-one prediction with con-current position correction. IEEE Transactions on Computers, 1999, 48(10): 298–305.

    Article  Google Scholar 

  12. Quach N, Flynn M. Leading one prediction—Implementation, generalization, and application. Technical Report CSL-TR-91-463, Stanford University, March 1991.

  13. Oklobdzija V. An implementation algorithm and design of a novel leading zero detector circuit. In Proc. 26th IEEE Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, October 26–28, 1992, pp.391–395.

  14. Oklobdzija V. An algorithmic and novel design of a leading zero detector circuit: Comparison with logic synthesis. IEEE Transactions on VLSI Systems, 1993, 2(1): 124–128.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100080, P.R. China

    Ge Zhang, Wei-Wu Hu & Zi-Chu Qi

  2. Graduate University of the Chinese Academy of Sciences, Beijing, 100039, P.R. China

    Ge Zhang, Wei-Wu Hu & Zi-Chu Qi

Authors
  1. Ge Zhang
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Wei-Wu Hu
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Zi-Chu Qi
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Ge Zhang.

Additional information

Supported by the National High Technology Development 863 Program of China under Grant Nos. 2002AA111100 and the National Basic Research 973 Program of China under Grant No. 2005CB321600.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Zhang, G., Hu, WW. & Qi, ZC. Parallel Error Detection for Leading Zero Anticipation. J Comput Sci Technol 21, 901–906 (2006). https://doi.org/10.1007/s11390-006-0901-3

Download citation

  • Received:

  • Revised:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11390-006-0901-3

Keywords

Search

Navigation