Abstract
The Godson-2G microprocessor is a high performance SOC which integrates a four-issue 64-bit high performance CPU core (called GS464), a DDR2/3 controller, a HyperTransport controller, a PCI/PCI-X controller, etc. It is physically implemented in 65 nm CMOS process and reaches the frequency of 1GHz with power consumption less than 4 W. The main challenges of Godson-2G physical implementation include nanometer process technology effects, high performance design targets, and tight schedule. This paper describes the key innovative features of physical design methodology which had been used in Godson-2G physical implementation, with particular emphasis on interconnect driven floorplan generation (ICD-FP), adapted boundary constraints design optimization (ABC-OPT), automatic register group clock tree generation methodology (ARG-CTS).
Similar content being viewed by others
References
Hu W, Zhao J, Zhong S, Yang X, Guidetti E, Wu C. Implementing a 1 GHz four-issue out-of-order execution microprocessor in a standard cell ASIC methodology. Journal of Computing Science and Technology, Jan. 2007, 22(1): 1–14.
Pham D et al . The design and implementation of a first-generation CELL processor. In ISSCC 2005, Digest of Technical Papers, San Francisco, USA, Feb. 10, 2005, pp.185–591.
Edman A, Svensson C. Timing closure through a globally synchronous, timing partitioned design methodology. In Proc. the 41st Design Automation Conference, San Diego, USA, June 7–11, 2004, pp.71–74.
Chen T C, Chang Y W, Lin S C. A new multilevel framework for large-scale interconnect-driven floorplanning. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Feb. 2008, 27(2): 286–294.
Adya S N, Markov I L. Fixed-outline floorplanning: Enabling hierarchical design. IEEE Trans. Very Large Scale Integration (VLSI) Systems, 2003, 11(6): 1120–1135.
Aurang Khan et al . A 90-nm power optimization methodology with application to the ARM 1136JF-S microprocessor. IEEE Journal of Solid-State Circuits, August 2006, 41(8): 1707–1717.
Chanodia I, Velenis D. Effects of parameter variations and crosstalk on H-tree clock distribution networks. In Proc. the 48th Midwest Symposium on Circuits and Systems (MWSCAS 2005), Cincinnati, USA, Aug. 7–10, 2005, pp.547–550.
Author information
Authors and Affiliations
Corresponding author
Additional information
Supported by the National High Technology Research and Development 863 Program of China under Grant No. 2007AA01Z114.
Rights and permissions
About this article
Cite this article
Zhao, JY., Liu, D., Huan, DD. et al. Physical Design Methodology for Godson-2G Microprocessor. J. Comput. Sci. Technol. 25, 225–231 (2010). https://doi.org/10.1007/s11390-010-9319-z
Received:
Revised:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11390-010-9319-z