Abstract
For the purpose of solving the shortcomings of low speed and high power consumption of asynchronous wrapper in conventional network on chips, this paper proposes a quasi delay-insensitive high-speed two-phase operation mode asynchronous wrapper. The metastable state in sampling data procedure can be avoided by detecting the write/read signal, which can be used to stop the clock. Empty/full level of the registers can be determined by detecting the pulse signal of the two-phase asynchronous register, and then control the wrapper to sample input/output data. Sender wrapper and receiver wrapper consist of C elements and threshold gates, which ensure the quasi delay-insensitive characteristics and enhance the robustness. Simulations under different technology corners are implemented based on SMIC 0.18 μm standard CMOS. Sender wrapper and receiver wrapper allow synchronous modules to work at the speed of 3.08 GHz and 2.98 GHz respectively with average dynamic power consumption of 1.727mW and 1.779mW. Its advantages of high-throughput, low-power, scalability and robustness make it a viable option for high-speed low-power interconnection of network-on-chip.
Similar content being viewed by others
References
Dally W J, Towles B. Route packets, not wires: On-chip interconnection networks. In Proc. 38th ACM Conf. Design Automation, Las Vegas, Nevada, Jun. 18-22, 2001, pp.684–689.
Benini L, Micheli G D. Networks on chips: A new SoC paradigm. Computer, 2002, 35(1): 70–78.
Wang J L, Xue Y B, Wang H X, Li C M, Wang D S. CCNoC: Cache-coherent network on chip for chip multiprocessors. J. Comput. Sci. & Technol., 2010, 25(2): 257–266.
Bainbridge J, Furber S B. CHAIN: A delay-insensitive chip area Interconnect. IEEE Micro, 2002, 22(5): 16–23.
Lines A. Asynchronous interconnect for synchronous SoC design. IEEE Micro, 2004, 24(1): 32–41.
Geer D. Is it time for clockless chips? Computer, 2005, 38(3): 18–21.
Teehan P, Greenstreet M, Lemieux G. A survey and taxonomy of GALS design styles. IEEE Design & Test of Computers, 2007, 24(5): 418–428.
Sheibanyrad A, Greiner A, Miro-Panades I. Multisynchronous and fully asynchronous NoCs for GALS architectures. IEEE Design & Test of Computers, 2008, 25(6): 572–580.
Krstic M, Grass E, Gurkaynak F K, Vivet P. Globally asynchronous, locally synchronous circuits: Overview and outlook. IEEE Design & Test of Computers, 2007, 24(5): 430–441.
Dobkin R R, Ginosar R. Two-phase synchronization with subcycle latency. Integration, the VLSI Journal, 2009, 42(3): 367–375.
Sheibanyrad A, Greiner PA. Two efficient synchronous ↔ asynchronous converters well-suited for networks-on-chip in GALS architectures. Integration, the VLSI Journal, 2008, 41(1): 17–26.
Beigne E, Vivet P. Design of on-chip and off-chip interfaces for a GALS NoC architecture. In Proc. the 12th International Symposium on Advanced Research in Asynchronous Circuits and Systems, Grenoble, Mar. 13-15, 2006, pp.172–181.
Yvain T, Edith B, Pascal V. Design and implementation of a GALS adapter for ANoC based architectures. In Proc. the 15th International Symposium on Asynchronous Circuits and Systems, Chapel Hill, USA, May 17-20, 2009, pp.13–22.
Beigne E, Clermidy F, Miermont S, Vivet P. Dynamic voltage and frequency scaling architecture for units integration within a GALS NoC. In Proc. the 2nd IEEE International Symposium on Networks-on-Chip, Newcastle Upon Tyne, UK, Apr. 7-11, 2008, pp.129–138.
Author information
Authors and Affiliations
Corresponding author
Additional information
Supported by the National Natural Science Foundation of China under Grant Nos. 60725415, 60971066, the National High-Tech Research and Development 863 Program of China under Grant Nos. 2009AA01Z258, 2009AA01Z260, and the National Science & Technology Important Project under Grant No. 2009ZX01034-002-001-005.
Rights and permissions
About this article
Cite this article
Guan, XG., Tong, XY. & Yang, YT. Quasi Delay-Insensitive High Speed Two-Phase Protocol Asynchronous Wrapper for Network on Chips. J. Comput. Sci. Technol. 25, 1092–1100 (2010). https://doi.org/10.1007/s11390-010-9390-5
Received:
Revised:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11390-010-9390-5