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TSV Minimization for Circuit — Partitioned 3D SoC Test Wrapper Design

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Abstract

Semiconductor technology continues advancing, while global on-chip interconnects do not scale with the same pace as transistors, which has become the major bottleneck for performance and integration of future giga-scale ICs. Three-dimensional (3D) integration has been proposed to sustain Moore’s law by incorporating through-silicon vias (TSVs) to integrate different circuit modules in the vertical direction, which is believed to be one of the most promising techniques to tackle the interconnect scaling problem. Due to its unique characteristics, there are many research opportunities, and in this paper we focus on the test wrapper optimization for the individual circuit-partitioned embedded cores within 3D System-on-Chips (SoCs). Firstly, we use existing 2D SoCs algorithms to minimize test time for individual embedded cores. In addition, vertical interconnects, i.e., TSVs that are used to construct the test wrapper should be taken into consideration as well. This is because TSVs typically employ bonding pads to tackle the misalignment problem, and they will occupy significant planar chip area, which may result in routing congestion. In this paper, we propose a series of heuristic algorithms to reduce the number of TSVs used in test wrapper chain construction without affecting test time negatively. It is composed of two steps, i.e., scan chain allocation and functional input/output insertion, both of which can reduce TSV count significantly. Through extensive experimental evaluations, it is shown that the test wrapper chain structure designed by our method can reduce the number of test TSVs dramatically, i.e., as much as 60.5 % reductions in comparison with the random method and 26 % in comparison with the intuitive method.

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References

  1. Davis J A, Venkatesan R, Kaloyeros A et al. Interconnect limits on gigascale integration (GSI) in the 21st century. Proceedings of the IEEE, 2001, 89(3): 305-324.

    Article  Google Scholar 

  2. Lewis D L, Lee H H S. Test circuit-partitioned 3D IC designs. In Proc. ISVLSI, May 2009, pp.139-144.

  3. Lee H-H S, Chakrabarty K. Test challenges for 3D integrated circuits. IEEE Design & Test of Computers, 2009, 26(5): 26-35.

    Article  Google Scholar 

  4. Marinissen E J. Test challenges for 3D-SICs: All the old, most of the recent, and then some new! In Proc. ITC, Nov. 2009.

  5. Marinissen E J, Arendsen R, Bos G et al. A structured and scalable mechanism for test access to embedded resuable cores. In Proc. ITC, Oct. 1998, pp.284-293.

  6. Iyengar V, Chakrabarty K, Marinissen E J. Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs. In Proc. the 39th DAC, Jun. 2002, pp.685-690.

  7. Huang Y, Reddy S M, Cheng W T et al. Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm. In Proc. ITC, Oct. 2002, pp.74-82.

  8. Loi I, Mitra S, Lee T H, Fujita S, Benini L. A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. In Proc. ICCAD, Nov. 2008, pp.598-602.

  9. Wu X, Falkenstern P, Xie Y. Scan chain design for threedimensional integrated circuits (3D ICs). In Proc. the 25th Int. Conf. Computer Design, Oct. 2007, pp.208-214.

  10. Chandran U, Zhao D. Thermal driven test access routing in hyper-interconnected three-dimensional system-on-chip. In Proc. the 24th Int. Symp. Defect and Fault Tolerance in VLSI Systems, Oct. 2009, pp.410-418.

  11. Noia B, Charabarty K, Xie Y. Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs. In Proc. ICCD, Oct. 2009, pp.70-77.

  12. Iyengar V, Chakrabarty K, Marinissen E J. Test wrapper and test access mechanism co-optimization for system-on-chip. In Proc. ITC, Oct. 2001, pp.1023-1032.

  13. Marinissen E J, Goel S K, Lousberg M. Wrapper design for embedded core test. In Proc. ITC, Oct. 2000, pp.911-920.

  14. International technology roadmap for semiconductors. http://www.itrs.net/links/2009ITRS/Home2009.htm, July 2012.

  15. Mak T M. Test challenges for 3D circuits. In Proc. the 12th IOLTS, Jul. 2006, p.79.

  16. Chen P Y, Wu C W, Kwai D M. On-chip TSV testing for 3D IC before bonding using sense amplification. In Proc. ATS, Nov. 2009, pp.450-455.

  17. Lewis D L, Lee H H S. Test strategies for 3D die-stacked integrated circuits. In Proc. DATE, Apr. 2009.

  18. Lewis D L, Lee H H S. A scan-island based design enabling pre-bond testability in die-stacked microprocessors. In Proc. ITC, Oct. 2007, pp.1-8.

  19. Marinissen E J, Zorian Y. Testing 3D chips containing through-silicon vias. In Proc. ITC, Nov. 2009, pp.1-11.

  20. Wu X, Chen Y, Chakrabarty K, Xie Y. Test-access mechanism optimization for core-based three-dimensional SOCs. In Proc. ICCD, Oct. 2008, pp.212-218.

  21. Jiang L, Huang L, Xu Q. Test architecture design and optimization for three-dimensional SoCs. In Proc. DATE, Apr. 2009, pp.220-225.

  22. Jiang L, Xu Q, Chakrabarty K, Mak T M. Layout-driven test-architecture design and optimization for 3D SoCs under prebond test-pin-count constraint. In Proc. ICCAD, Nov. 2009, pp.191-196.

  23. Huang Y J, Li J F. Testability exploration of 3-D RAMs and CAMs. In Proc. ATS, Nov. 2009, pp.397-402.

  24. Zhao X, Lewis D L, Lee H H S, Lim S K. Pre-bond testable low-power clock tree design for 3D stacked ICs. In Proc. ICCAD, Nov. 2009, pp.184-190.

  25. Roy S K, Ghosh S, Rahaman H, Giri C. Test wrapper design for 3D system-on-chip using optimized number of TSVs. In Proc. ISED, Dec. 2010, pp.197-202.

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Authors and Affiliations

  1. State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100190, China

    Yuan-Qing Cheng (Student Member, CCF, IEEE), Lei Zhang (Member, CCF, IEEE), Yin-He Han (Member, CCF, ACM, IEEE) & Xiao-Wei Li (Member, CCF, ACM, IEEE)

  2. Graduate University of Chinese Academy of Sciences, Beijing, 100049, China

    Yuan-Qing Cheng (Student Member, CCF, IEEE)

Authors
  1. Yuan-Qing Cheng
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  2. Lei Zhang
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  3. Yin-He Han
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  4. Xiao-Wei Li
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Corresponding author

Correspondence to Yin-He Han.

Additional information

This work was supported in part by the National Basic Research 973 Program of China under Grant No. 2011CB302503 and the National Natural Science Foundation of China under Grant Nos. 60806014, 61076037, 60906018, 61173006, 60921002, 60831160526.

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Cheng, YQ., Zhang, L., Han, YH. et al. TSV Minimization for Circuit — Partitioned 3D SoC Test Wrapper Design. J. Comput. Sci. Technol. 28, 119–128 (2013). https://doi.org/10.1007/s11390-013-1316-6

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  • DOI: https://doi.org/10.1007/s11390-013-1316-6

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