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A glance of technology efforts for design-for-manufacturing in nano-scale CMOS processes

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Abstract

This paper overviews design for manufacturing (DFM) for IC design in nano-CMOS technologies. Process/device issues relevant to the manufacturability of ICs in advanced CMOS technologies will be presented first before an exploration on process/device modeling for DFM is done. The discussion also covers a brief introduction of DFM-aware of design flow and EDA efforts to better handle the design-manufacturing interface in very large scale IC design environment.

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References

  1. Maly W. IC design in high cost nanometer technologies era. In: Design Automation Conference. Las Vegas, NV: IEEE Solid-State Society, 2001. 9–14

    Google Scholar 

  2. Fichtner W, Pramanik D, Bomholt L. Closing the gap between manufacturing and design. In: 2005 Electronic Design Progress Symposium. Monterey California: IEEE Solid-State Circuit Society, 2005. 64–68

    Google Scholar 

  3. Sifri J. Statistical design can increase IC yield. EETimes, 02/24/2003

  4. Burek D. True design-for-manufacturability critical to 65-nm design success. EETimes, 11/07/2007

  5. Verghese N, Hurat P. DFM reality in sub-nanometer IC design. In: Asia and South Pacific Design Automation Conference, IEEE Solid-State Circuit Society, 2007. 226–231

  6. Guardiani C, Dragone N, McNamara P. Proactive design for manufacturing (DFM) for nanometer SoC designs. In: Proceedings of the IEEE Custom Integrated Circuits Conference. San Jose, California: IEEE Solid-State Circuit Society, 2004. 309–316

    Google Scholar 

  7. Kibarian J. Enabling true design for manufacturability. In: Sixth International Symposium on Quality of Electronic Design. March 26–28, San Jose CA: IEEE Computer Society, 2005, 15

    Chapter  Google Scholar 

  8. Kahng A B. Design challenges at 65 nm and beyond. In: Design, Automation & Test in Europe Conf. & Exhibition, Nice, France, IEEE Computer Society, 2007, 1–2

    Chapter  Google Scholar 

  9. Chang K J. Accurate on-chip variation modeling to achieve design for manufacturability. In: Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC’04), Banff, Canada, IEEE Circuit and System Society, 2004. 219–222

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Correspondence to YuHua Cheng.

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Supported by the National Natural Science Foundation of China (Grant No. 60736030)

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Cheng, Y. A glance of technology efforts for design-for-manufacturing in nano-scale CMOS processes. Sci. China Ser. F-Inf. Sci. 51, 807–818 (2008). https://doi.org/10.1007/s11432-008-0054-9

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  • DOI: https://doi.org/10.1007/s11432-008-0054-9

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