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Challenges of 22 nm and beyond CMOS technology

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Abstract

It is predicted that CMOS technology will probably enter into 22 nm node around 2012. Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and needs some significant changes of the technology, as well as integration of the advanced processes. This paper will review the key processing technologies which can be potentially integrated into 22 nm and beyond technology nodes, including double patterning technology with high NA water immersion lithography and EUV lithography, new device architectures, high K/metal gate (HK/MG) stack and integration technology, mobility enhancement technologies, source/drain engineering and advanced copper interconnect technology with ultra-low-k process.

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Authors and Affiliations

  1. Department of Microelectronics, Peking University, Beijing, 1000871, China

    Ru Huang, JinFeng Kang, Xia An, Yu Tian, RunSheng Wang, LiangLiang Zhang, Xing Zhang & YangYuan Wang

  2. Semiconductor Manufacturing International Corporation (SMIC), Beijing, 100176, China

    HanMing Wu, DeYuan Xiao & XueLong Shi

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  1. Ru Huang
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  2. HanMing Wu
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Correspondence to Ru Huang.

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Supported by the National Natural Science Foundation of China (Grant Nos. 60625403, 90207004), and the National Basic Research Program of China (Grant No. 2006CB302701)

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Huang, R., Wu, H., Kang, J. et al. Challenges of 22 nm and beyond CMOS technology. Sci. China Ser. F-Inf. Sci. 52, 1491–1533 (2009). https://doi.org/10.1007/s11432-009-0167-9

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