Abstract
Test power of VLSI systems has become a challenging issue nowadays. The scan shift power dominates the average test power and restricts clock frequency of the shift phase, leading to excessive thermal accumulation and long test time. This paper proposes a scan chain design technique to solve the above problems. Based on weighted transition metric (WTM), the proposed extended WTM (EWTM) that is utilized to guide the scan chain design algorithm can estimate the scan shift power in both the shift-in and shift-out phases. Moreover, the wire length overhead of the proposed scan chain design can also be reduced by the proposed distance of EWTM (DEWTM) metric. Experimental results confirm that the proposed approach can significantly reduce scan shift power with low wire length overhead.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Crouch A. Design-for-Test for Digital ICs and Embedded Core Systems. Upper Saddle River, NJ: Prentice Hall, 1999
Girard P. Survey of low-power testing of VLSI circuits. In: Proc. of IEEE Design and Test of Computers, 2002. 82–92
Zorian Y. A distributed BIST control scheme for complex VLSI devices. In: Proc. of VLSI Test Symposium, Guam, 1993. 4–9
Whetsel L. Adapting scan architectures for low power operation. In: Proc. of International Test Conference, Atlantic, 2000. 863–872
Rosinger P, Al-Hashimi B M, Nicolici N. Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction. IEEE Trans Comput-Aid Design Integ Circ Syst, 2004, 23: 1142–1153
Sankaralingam R, Touba N A. Inserting test points to control peak power during scan testing. In: Proc. of International Symposium on Defect and Fault Tolerance in VLSI Systems, Vancouver, 2002. 138–146
Elm M, Wunderlich H J, Imhof M E, et al. Scan chain clustering for test power reduction. In: Proc. of Design Automation Conference, San Francisco, 2008. 828–833
Xiang D, Fujiwara H. Nonscan design for testability for synchronous sequential circuits based on conflict resolution. IEEE Trans Comput, 2003, 52: 1063–1075
Xiang D, Hu D, Xu Q, et al. Low-power scan testing for test data compression using a routing-driven scan architecture. IEEE Trans Comput-Aid Design, 2009, 28: 1101–1105
Hu Y, Li C, Li J, et al. Test data compression based on clustered random access scan. In: Proc. of Asian Test Symposium, Fukuoka, 2006. 231–236
Bonhomme Y, Girard P, Guiller L, et al. Efficient scan chain design for power minimization during scan testing under routing constraint. In: Proc. of International Test Conference, Charlotte, 2003. 488–493
Badereddine N, Girard P, Pravossoudovitch S, et al. Scan cell reordering for peak power reduction during scan test cycles. IFIP Int Fed Inf Process, 2007, 240: 267–281
Wu Y Z, Chao M C T. Scan-chain reordering for minimizing scan-shift power based on non-specified test cubes. In: Proc. of VLSI Test Symposium, San Diego, 2008. 147-154
Li J, Hu Y, Li X. A scan chain adjustment technology for test power reduction. In: Proc. of Asian Test Symposium, Fukuoka, 2006. 11–16
Sinanoglu O, Orailoglu A. Scan power minimization through stimulus and response transformations. In: Proc. of Design, Automation and Test in Europe Conference and Exhibition, Paris, 2004. 404–409
Butler K M, Saxena J, Jain A, et al. Minimizing power consumption in scan testing-pattern generation and DFT techniques. In: Proc. of International Test Conference, Charlotte, 2004. 355–364
Remersaro S, Lin X, Zhang Z, et al. Preferred fill: a scalable method to reduce capture power for scan based designs. In: Proc. of International Test Conference, Santa Clara, 2006. 32.3
Wen X, Yamashita Y, Kajihara S, et al. On low-capture-power test generation for scan testing. In: Proc. of IEEE VLSI Test Symposium (VTS), Palm Springs, CA, USA, 2005. 265–270
Li J, Xu Q, Hu Y, et al. iFill: an impact-oriented X-filling method for shift- and capture-power reduction in at-speed scan-based testing. In: Proc. of Design, Automation, and Test in Europe, Munich, 2008. 1184–1189
Sankaralingam R, Oruganti R R, Touba N A. Static Compaction techniques to control scan vector power dissipation. In: Proc. of VLSI Test Symposium, Montreal, 2000. 35–40
Hamzaoglu I, Patel J. Test set compaction algorithms for combinational circuits. In: Proc. of International Test Conference, Washington DC, 1998. 283–289
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Li, J., Hu, Y. & Li, X. Scan chain design for shift power reduction in scan-based testing. Sci. China Inf. Sci. 54, 767–777 (2011). https://doi.org/10.1007/s11432-011-4205-z
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11432-011-4205-z