Skip to main content
SpringerLink
Log in

3D integration review

  • Special Issue
  • Published:
Science China Information Sciences Aims and scope Submit manuscript

Abstract

3-D integration delivers value by increasing the volumetric transistor density with the potential benefit of shorter electrical path lengths through use of the shorter third dimension. Several researchers have studied various aspect of 3Di such as bonding level, through silicon via processes and integration, thermomechanical reliability of the vias, and the impact of the vias on devices. In this paper, we review some of the literature with a view to understanding the key options and challenges in 3Di. We also discuss some important applications of this technology, and the constraints that have to be overcome to make it work.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Morgan T P. IBM’s zEnterprise 196 CPU: Cache is king-the fastest CPU in the world. http://www.theregister.co.uk/2010/07/23/ibmz196mainframeprocessor/

  2. Zeng A, Lu J, Rose K, et al. First order performance prediction of cache memory with wafer-level 3D integration. IEEE Des Test Comput, 2005, 22: 548–555

    Article  Google Scholar 

  3. Black B, Annavaram M, Brekelbaum N, et al. Die stacking (3D) microarchitecture. In: The 39th Annual IEEE/ACM Int’l Symposium on Microarchitecture, 2006. 469–479

  4. Peltola T, Mansikkamaki P, Ristolainen E O. 3D integration of electronics and mechanics. In: Proc. of the Int’l Symposium on Advanced Packaging Materials, 2005. 5–8

  5. Charlet B, Cioccio D, LeDuc P. Enabling technologies for 3D system on chip (SOC) integration and examples of 3D integrated structures. In: Proc. of the IEEE Int’l Conference on Integrated Circuit Design and Technology, 2007. 1

  6. Yole Development, Market Report, Nov 2007

  7. Bougard B, Marchal P, Benini L, et al. Hot topic-3D integration or how to scale in the 21st century. In: Design, Automation and Test, 2008. 1516

  8. Sadaka M, Radu I, DiCioccio L. 3D integration-advantages, enabling technologies & applications. In: Proc. of the IEEE Int’l Conference on IC Design and Technology, 2010. 106–109

  9. Choudhury D. 3D integration technologies for emerging Microsystems. In: Proceedings of the IMS, 2010

  10. Koester S, Young A M, Yu R R, et al. Wafer-level 3D integration technology. Special Issue of IBM J Res Dev, 2008, 52: 583–597

    Google Scholar 

  11. Ohba T. 3D large scale integration technology using wafer on wafer (WOW) stacking. In: Proc of the IEEE Int’l Interconnect Technology Conference, 2009

  12. Topol A W, LaTulipe D C, Shi L, et al. Enabling SOI-based assembly technology for 3D integrated circuits (ICs). In: Proceedings of the IEEE International Electron Devices Meeting, Washington, DC, 2005. 352–355

  13. Iyer S S, Auberton-Herve A J. Silicon wafer bonding technoloy for VLSI and MEMS applications. In: EMIS Processing Series 1, INSPEC, 2002

  14. Ziptronix, Inc. ZiBond direct wafer bonding technology. see http://www.ziptronix.com/techo/zibond.html

  15. University of Texas at Arlington, Automation and Robotics Research Institute, http://arri.uta.edu/micromanufacturing/micropackaging/3Dpackaging.html

  16. Williams G, O’Hara P, Moore J, et al. A review of wafer bonding materials and characterizations to enable wafer thinning, backside processing, and laser dicing. In: Proceedings of the IEEE Electronic Components and Technology Conference, 2009

  17. Huyghebaert C, Van Olmen J, Civale Y, et al. Cu to Cu interconnect using 3D TSV and wafer to wafer thermocompression bonding. In: Proc. of the IEEE Int’l Interconnect Technology Conference, 2010. 1–3

  18. Webb R. Temporary bonding enables new processes requiring ultra-thin wafers. In: Solid State Technology, www.solidstate.com, February 2010

  19. Bieck F, Spiller S, Molina F, et al. Carrierles design for handling and processing of ultrathin wafers. In: Proc. of the IEEE Electronic Components and Technology Conference, 2010. 316–322

  20. Sakuma K, Andry P S, Tsang C K, et al. 3D chip-stacking technology with TSV’s and low-volume lead-free interconnections. Special Issue of IBM J Res Dev, 2008, 52: 611–621

    Google Scholar 

  21. Dang B, Wright S L, Andry P S, et al. 3D chip stacking with C4 technology. Special Issue of IBM J Res Dev, 2008, 52: 599–609

    Google Scholar 

  22. Van Olmen J, Coenen J, Dehaene W, et al. 3D stacked IC demonstrator using hybrid collective die-to-wafer bonding with copper TSV. In: Proceedings of the IEEE Electronic Components and Technology Conference, 2009

  23. Leduc P, Assous M, DiCioccio L, et al. First integration of Cu TSV using die-to-wafer direct bonding and planarization. In: Proceedings of the IEEE Electronic Components and Technology Conference, 2009

  24. Andry P S, Tsang C K, Webb B C, et al. Fabrication and characterization of robust TSVs for silicon-carrier applications. Special Issue of IBM J Res Dev, 2008, 52: 571–581

    Google Scholar 

  25. Joseph A J, Gillis J D, Doherty M, et al. TSV’s enable next-generation SiGe power amplifiers for wireless communications. Special Issue of IBM J Res Dev, 2008, 52: 635–648

    Google Scholar 

  26. Katti G, Mercha A, Van Olmen J, et al. 3D stacked ICs using Cu TSVs and die to wafer collective bonding. In: Proc. of the IEEE Int’l Electron Devices Meeting, 2009. 1–4

  27. Alapati R, Travaly Y, Van Olemn J, et al. TSV metrology and inspection challenges. In: IEEE 3D System Integration Conference, 2009

  28. Buchanan K, Burgess S, Giles K, et al. Etch, dielectrics and metal barrier-seed for low temperature TSV processing. In: IEEE 3D System Integration Conference, 2009

  29. Yoon S W, Yang D W, Koo J H, et al. 3D TSV processes and its assembly/packaging technology. In: IEEE 3D System Integration Conference, 2009

  30. Teh W H, Caramto R, Arkalgud S, et al. Magnetically-enhanced capacitively-coupled plasma etching for 300 mm waferscale fabrication of Cu TSV’s for 3D logic integration. In: Proc. of the IEEE Int’l Interconnect Technology Conference, 2009. 53–55

  31. Kaiho Y, Ohara Y, Takeshita H, et al. 3D integration technology for 3D stacked retinal chip. In: IEEE 3D System Integration Conference, 2009

  32. Dukovic J, Ramaswami S, Pamarthy S, et al. TSV technology for 3D integration. In: IEEE Memory Workshop, 2010. 1–2

  33. Li H Y, Liao E, Pang X F, et al. Fast electroplating TSV process development for the via-last approach. In: Proc. of the IEEE Electronic Components and Technology Conference, 2010. 777–780

  34. Chua T T, Ho S W, Li H Y, et al. 3D interconnection process development and integration with low stress TSV. In: Proc. of the IEEE Electronic Components and Technology Conference, 2010. 798–802

  35. LimB O, Choi K S, Eom Y S, et al. Optimized TSV process using bottoms-up electroplating without wafer cracks. In: Proc. of the IEEE Electronic Components and Technology Conference, 2010. 1642–1646

  36. Xie B, Shi X Q, Chung C H, et al. Novel sequential electro-chemical and thermo-mechanical simulation methodology for annular TSV design. 3D TSV processes and its assembly/Packaging technology. In: Proc. of the IEEE Electronic Components and Technology Conference, 2010. 1166–1172

  37. Malta D, Gregory C, Temple D, et al. Integrated process for defect-free copper plating and chemical-mechanical polishing of TSV’s for 3D development. In: Proc. of the IEEE Electronic Components and Technology Conference, 2010. 1769–1775

  38. Inoue F, Yokoyama T, Miyake H, et al. Conformal deposition of electroless barrier and seed layers. In: Proc. of the IEEE Int’l Interconnect Technology Conference, 2010. 1–2

  39. Archard D, Giles K, Price A, et al. Low temperature PECVD of dielectric films for TSV applications. In: Proc. of the IEEE Electronic Components and Technology Conference, 2010. 764–768

  40. Kawano M, Takahashi N, Komuro M, et al. Low-cost TSV process using electroless Ni plating for 3D stacked DRAM. In: Proc. of the IEEE Electronic Components and Technology Conference, 2010. 1094–1099

  41. Bouchoucha M, Chausse P, Henry D, et al. Process solutions and polymer materials for 3D-WLP TSV filling. In: Proc. of the IEEE Electronic Components and Technology Conference, 2010. 1696–1698

  42. Huyghebaert C, Van Olmen J, Chukwadi O, et al. Enabling 10 μm pitch hybrid Cu-Cu IC stacking with TSVs. In: Proc. of the IEEE Electronic Components and Technology Conference, 2010. 1083–1087

  43. Craigie C J D, Sheehan T, Johnson V N, et al. Polymer thickness effects on Bosch etch profiles. Vac Sci Technol B, 2002, 20: 2229–2232

    Article  Google Scholar 

  44. Kok K W, Yoo WJ, Sooriakumar K, et al. Investigation of in situ trench etching process and Bosch process for fabricating high-aspect-ration beams for micromechanical systems. J Vac Sci Tech B: Microelectron Nanometer Structures, 2002, 20: 1878–1883

    Article  Google Scholar 

  45. Volant R, Farooq M G. Coaxial TSV for 3D applications with polyimide dielectric. In: Symposium on Polymers for Microelectronics Conference, 2010

  46. Okoro C, Yang Y, Vandevelde B, et al. Extraction of the appropriate material property for realistic modeling of TSVs using μ-Raman spectroscopy. In: Proc. of the IEEE Int’l Interconnect Technology Conference, 2008. 16–18

  47. Mercha A, Redolfi A, Stucchi M, et al. Impact of thinning and TSV proximity on high-k/metal gate first CMOS performance. In: Proc. of the IEEE VLSI Technology Conference, 2010. 109–110

  48. Khan N, Alam S M, Hassoun S. TSV-induced noise characterization and noise mitigation using coaxial TSVs. In: Proceedings of the IEEE Electronic Components and Technology Conference, 2009

  49. Yang Y, Katti G, Labie R, et al. Electrical evaluation of 130-nm MOSFETs with TSV proximity in 3D-SIC structure. In: Proc. of the IEEE Int’l Interconnect Technology Conference, 2010. 1–3

  50. Okoro C, Gonzales M, Vandevelde B, et al. Prediction of the influence of induced stresses in silicon on CMOS Performance in a Cu-through-via interconnect technolog. In: Proc. of the IEEE Conference on Thermal, Mechanical and Multi-Physics Simulation Experiments in Microelectronics and Micro-Systems, 2007. 1–7

  51. Ohara Y, Noriki A, Sakuma K, et al. 10 m fine pitch Cu/Sn micro-bumps for 3-D super-chip Stack. In: IEEE 3D System Integration Conference, 2009

  52. Wright S L, Polastre R, Gan H, et al. Characterization of micro-bump C4 interconnects for Si-carrier SOP applications. In: Proceedings of the IEEE Electronic Components and Technology Conference, 2009. 633–640

  53. Yoon S W, Ku J H, Suthiwongsunthorn N, et al. Fabrication and packaging of microbump interconnections for 3D TSV. In: IEEE 3D System Integration Conference, 2009

  54. Horibe A, Yamada F. Advanced 3D chip stack process for thin dies with fine pitch bumps using pre-applied inter chip fill. In: IEEE 3D System Conference, 2009

  55. Agarwal R, Zheng W, Limaye P, et al. Cu/Sn microbumps interconnect for 3D TSV chip stacking. In: Proceedings of the IEEE Electronic Components and Technology Conference, 2010. 858–863

  56. Sri-Jayantha S M, McVicker G, Bernstein K, et al. Thermomechanical modeling of 3D electronic packages. Special Issue of IBM J Res Dev, 2008, 52: 623–634

    Google Scholar 

  57. Emma P G, Kursun E. Is 3D chip technology the next growth engine for performance improvement? Special Issue of IBM J Res Dev, 2008, 52: 541–552

    Google Scholar 

  58. Chen A, Song B, Wang X, et al. Thermo-mechanical reliability analysis of 3D stacked-die packaging with TSV. In: IEEE 11th Int’l Conference on Electronic Packaging Technology & High Density Packaging, 2010. 102–107

  59. Amagai M, Suzuki Y. TSV stress and modeling. In: Proc. of the IEEE Electronic Components and Technology Conference, 2010. 1273–1280

  60. Lu K H, Ryu S K, Zhao Q, et al. Thermal stress induced delamination of TSVs in 3D interconnects. In: Proc. of the IEEE Electronic Components and Technology Conference, 2010. 40–45

  61. Sunohara M, Sakaguchi H, Takano A, et al. Studies on electrical performance and thermal stress of a silicon interposer with TSVs. In: Proceedings of the IEEE Electronic Components and Technology Conference, 2010. 1088–1093

  62. Pang X F, Chua T T, Li H Y, et al. Characterization and management of wafer stress for various pattern Densities in 3D integration technology. In: Proc. of the IEEE Electronic Components and Technology Conference, 2010. 1866–1869

  63. Trigg A D, Yu L H, Zhang X, et al. Design and fabrication of a reliability test chip for 3D-TSV. In: Proc. of the IEEE Electronic Components and Technology Conference, 2010. 79–83

  64. Suntharalingam V, Rathman D, Prigozhin G, et al. Back-illuminated three-dimensionally integrated CMOS image sensors for scientific applications. In: Proc of SPIE Vol. 6690, 2007. 669009-1–669009-9

    Google Scholar 

  65. Gupta S, Hilbert M, Hong S, et al. Techniques for producing 3D ICs with high-density interconnect. In: VLSI Multi-Level Interconnection Conference, 2004

  66. Patti R. Lessons learned in the quest for 3D products. In: IMAPS Global Business Council, March 2009

  67. Garrou P. Insights from the leading edge. www.electroiq.com/index/packaging, October 2010

  68. Yole Development Market Report. Advanced Packaging: 3D IC and TSV Interconnects 2010

  69. Elpida, PTI, and UMC partner on 3D IC integration development for Advanced technologies including 28 nm. www.elpida.com, June 2010

  70. Samsung develops 3D memory package that greatly improves performance using less space. www.samsung.com, April 2006

  71. Sematech’s 3D interconnect program. www.sematech.org, 2010

  72. Jiang T, Shijian L. 3D integration-present and future. In: Proc. of the IEEE Electronic Components and Technology Conference, 2008. 373–378

  73. IBM work on 3D chip stacking will take Moore’s Law to 2025. www.nextbigfuture.com, March 2010

  74. Toshiba Eyes 3D memory chips with new factory investment. www.pcworld.com, May 2010

  75. Kujala K. Memory stacking to TSV? In: Semicon, Taiwan, 2010

  76. Mirkarimi L, Huynh M, Savalia P, et al. 3D interconnects for dense die stack packages. In: IEEE 3D System Integration Conference, 2009

  77. Fritzsch T, Mrobko R, Baumgartner T, et al. 3D thin chip integration technology-from technology development to application. In: IEEE 3D System Integration Conference, 2009

  78. Kang U, Chung H J, Heo S, et al. 8 Gb 3D DDR3 DRAM using through-silicon-via technology. In: IEEE ISSCC, 2009. 130–131, 131a

Download references

Author information

Authors and Affiliations

  1. IBM Corporation, Semiconductor Research & Development Center, Hopewell Junction, New York, NY, 12533, USA

    Mukta G. Farooq & Subramanian S. Iyer

Authors
  1. Mukta G. Farooq
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Subramanian S. Iyer
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Mukta G. Farooq.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Farooq, M.G., Iyer, S.S. 3D integration review. Sci. China Inf. Sci. 54, 1012–1025 (2011). https://doi.org/10.1007/s11432-011-4226-7

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11432-011-4226-7

Keywords

Search

Navigation