Abstract
In this paper, a new tunneling field effect transistor with comb-shaped gate (CG-TFET) is proposed and experimentally demonstrated. Source implantation masked by the comb-shaped gate can result in combshaped channel region. With this comb-shaped gate configuration, increased tunneling area can be obtained and hence higher on-state current without area penalty. Moreover, an optimized CG-TFET with silicide source is fabricated to further improve the on-state current by introducing Schottky barrier tunneling current which is much more efficient than band-to-band tunneling. In addition, the electron barrier in the comb-shaped channel region is raised due to the self depleted effect, which can effectively suppress the Schottky injection leakage from the silicide source in the off-state. 1.5 orders of magnitude higher than conventional TFET with the same footprint on-state current and more than 106 on-off current ratio can be achieved.
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References
Bjork M T, Knoch J, Schmid H, et al. Silicon nanowire tunneling field-effect transistors. Appl Phys Lett, 2008, 92: 193504–193506
Verhulst A S, Vandenberghe W G, Maex K, et al. Tunnel field-effect transistor without gate-drain overlap. Appl Phys Lett, 2007, 91: 053102–053104
Toh E H, Wang G H, Samudra G, et al. Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications. J Appl Phys, 2008, 103: 104504
Verhulst A S, Vandenberghe W G, Maex K, et al. Boosting the on-current of a n-channel nanowire tunnel field-effect transistor by source material optimization. J Appl Phys, 2008, 104: 064514
Verhulst A S, Vandenberghe W G, Maex K, et al. Complementary silicon-based heterostructure tunnel-fets with high tunnel rates. IEEE Electr Device L, 2008, 29: 1398–1401
Mayer F, Royer C L, Damlencourt J F, et al. Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible tunnel FET performance. In: IEDM, San Francisco, 2008. 163–166
Chen Z X, Yu H Y, Singh N, et al. Demonstration of tunneling FETs based on highly scalable vertical silicon nanowires. IEEE Electr Device L, 2009, 30: 754–756
Nah J, Liu E S, Varahramyan K M, et al. Ge-SixGe1-x core-shell nanowire tunneling field-effect transistors. IEEE Trans Electron Dev, 2010, 57: 1883–1888
Nagavarapu V, Jhaveri R, Woo J C S. The tunnel source (PNPN) n-MOSFET: a novel high performance transistor. IEEE Trans Electron Dev, 2008, 55: 1013–1019
Hu C M, Chou D, Patel P, et al. Green transistor—a V DD scaling path for future low power ICs. In: VLSI TSA, Xinzhu, 2008. 14–15
Huang Q Q, Zhan Z, Huang R, et al. Self-depleted T-gate schottky barrier tunneling FET with low average subthreshold slope and high ION/IOFF by gate configuration and barrier modulation. In: IEDM, Washington, 2011. 382–385
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Zhan, Z., Huang, Q., Huang, R. et al. A comb-gate silicon tunneling field effect transistor with improved on-state current. Sci. China Inf. Sci. 56, 1–6 (2013). https://doi.org/10.1007/s11432-012-4713-5
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DOI: https://doi.org/10.1007/s11432-012-4713-5