Abstract
This paper presents a low-power high linearity ΣΔ analog-to-digital converter (ADC) for audio applications. By adopting low noise large output swing operational amplifiers in a 2–1 cascaded modulator, not only can the noise floor be reduced, but the input signal range can also be enlarged. A low-power, area-efficient digital decimation filter was also designed to decrease the area and the power cost. The ADC was fabricated in the SMIC 65 nm single-poly-eight-metal (1P8M) mixed-signal complementary metal-oxide-semiconductor (CMOS) process with a die area of 0.36 mm2. Measurement results showed that a 90 dB peak signal to noise plus distortion ratio (SNDR) and a 93 dB dynamic range (DR) were achieved over the 22.05 kHz audio band. The power dissipation was 2.2 mW from 1.2 V power supply, which is suitable for audio codec applications.
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References
Cornelissens K, Steyaert M. A 1-V 84-dB DR 1-MHz bandwidth cascade 3–1 Delta-Sigma ADC in 65-nm CMOS. In: Proceedings of ESSCIRC, Athens, 2009. 332–335
Libin Yao, Michiel S J, Steyaert. A 1-V 140-μW 88-dB audio Sigma-Delta modulator in 90-nm CMOS. IEEE J Solid-State Circuit, 2004, 39: 1809–1818
Ranjbar M, Lahiji G R. A low power third order Delta-Sigma modulator for digital audio applications. In: IEEE International Symposium on Circuits and Systems, Island of Kos, 2006. 4759–4762
Yavari M, Shoaei O, Afzali-Kusha A. A very low-voltage, low-power and high resolution Sigma-Delta modulator for digital audio in 0.25 μm CMOS. In: Proceedings of the 2003 International Symposium on Circuits and Systems, Bangkok, 2003. 1045–1048
Lei J M, Dai X W. Modeling non-idealities of Sigma Delta ADC in Simulink. In: ICCCAS International Conference on Communications, Circuits and Systems, Fujian, 2008. 1040–1043
Banu M, Khoury J M, Tsividis Y. Fully differential operational amplifiers with accurate output balancing. IEEE J Solid-State Circuit, 1988, 23: 1410–1414
Zhang X, Pei W H, Huang B J. A low-noise fully-differential CMOS preamplifier for neural recording applications. Sci China Inf Sci, 2012, 55: 441–452
Fayomi C J B, Robers G W, Sawan M A. Low-voltage CMOS analog bootstrapped switch for sample-and-hold circuit: design and chip characterization. In: IEEE International Symposium on Circuits and Systems, Kobe, 2005. 2200–2203
Liu H X, Yuan B. Low-power design and application based on CSD optimization for a fixed coefficient multiplier. Sci China Inf Sci, 2011, 54: 2443–2453
Brandt B P, Wooley B A. A low-power, area-efficient digital filter for decimation and interpolation. IEEE J Solid-State Circuit, 1994, 29: 679–687
Aparicio R, Hajimiri A. Capacity Limits and Matching Properties of Integrated Capacitors. IEEE J Solid-State Circuit, 2002, 37: 384–393
Jian Y W, Zhang Z Y, Subramoniam R. A 107.4 dB SNR multi-bit Sigma Delta ADC with 1-PPM THD at 0.12 dB from full scale input. IEEE J Solid-State Circuit, 2009, 44: 3060–3066
Choi M-Y, Lee S-N. A 101-dB SNR hybrid Delta-Sigma audio ADC using post integration time control. In: IEEE Custom Intergrated Circuits Conference, San Jose, 2008. 89–92
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Liao, L., Sun, Y., Han, Y. et al. A 65-nm low-power high-linearity ΣΔ ADC for audio applications. Sci. China Inf. Sci. 57, 1–7 (2014). https://doi.org/10.1007/s11432-013-4784-y
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DOI: https://doi.org/10.1007/s11432-013-4784-y