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A low offset chopper amplifier with three-stage nested Miller configuration

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Abstract

A low offset, low noise chopper amplifier for sensor system application is presented. Low 1/f noise is achieved by employing chopper technique, and low offset is achieved by employing residual offset suppression circuit. The open-loop gain is extended using three-stage nested Miller configuration. The chip was implemented in 0.5 μm 2P3M CMOS process. The amplifier is featured by an open-loop gain of 135 dB and a GBW of 3 MHz. The measured offset voltage is 3 μV, and the equivalent input noise power spectrum density at 1 Hz is 96 nV / \(\sqrt {Hz} \).

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Authors and Affiliations

  1. Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, 100029, China

    ZhuoLei Huang, WeiBing Wang, Fan Jiang & DaPeng Chen

  2. Smart Integrated Sensor Engineering Center, Jiangsu Research and Development Center for Internet of Things, Wuxi, 214135, China

    WeiBing Wang

Authors
  1. ZhuoLei Huang
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  2. WeiBing Wang
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  3. Fan Jiang
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  4. DaPeng Chen
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Correspondence to WeiBing Wang.

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Huang, Z., Wang, W., Jiang, F. et al. A low offset chopper amplifier with three-stage nested Miller configuration. Sci. China Inf. Sci. 57, 1–7 (2014). https://doi.org/10.1007/s11432-013-4903-9

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  • DOI: https://doi.org/10.1007/s11432-013-4903-9

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