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A high speed multi-level-parallel array processor for vision chips

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Abstract

This paper proposes a high speed multi-level-parallel array processor for programmable vision chips. This processor includes 2-D pixel-parallel processing element (PE) array and 1-D row-parallel row processor (RP) array. The two arrays both operate in a single-instruction multiple-data (SIMD) fashion and share a common instruction decoder. The sizes of the arrays are scalable according to dedicated applications. In PE array, each PE can communicate not only with its nearest neighbor PEs, but also with the next near neighbor PEs in diagonal directions. This connection can help to speed up local operations in low-level image processing. On the other hand, global operations in mid-level processing are accelerated by the skipping chain and binary boosters in RP array. The array processor was implemented on an FPGA device, and was successfully tested for various algorithms, including real-time face detection based on PPED algorithm. The results show that the image processing speed of proposed processor is much higher than that of the state-of-the-arts digital vision chips.

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Authors and Affiliations

  1. State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing, 100083, China

    Cong Shi, Jie Yang & NanJian Wu

  2. Department of Electronic Engineering, Tsinghua University, Beijing, 100084, China

    Cong Shi & ZhiHua Wang

  3. Institute of Microelectronics, Tsinghua University, Beijing, 100084, China

    ZhiHua Wang

Authors
  1. Cong Shi
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  2. Jie Yang
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  3. NanJian Wu
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  4. ZhiHua Wang
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Correspondence to NanJian Wu.

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Shi, C., Yang, J., Wu, N. et al. A high speed multi-level-parallel array processor for vision chips. Sci. China Inf. Sci. 57, 1–12 (2014). https://doi.org/10.1007/s11432-013-4969-4

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  • DOI: https://doi.org/10.1007/s11432-013-4969-4

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