References
Doris B, Desalvo B, Cheng K, et al. Planarn Fully- Depleted-Silicon-On-Insulator technologies: toward the 28 nm node and beyond. Solid-State Electron, 2015, 117: 37–59
Noel J P, Thomas O, Jaud MA, et al. Multi-VT UTBB FDSOI device architectures for low-power CMOS circuit. IEEE Trans Electron Dev, 2011, 58: 2473–2482
Yin L X, Shen L, Jiang H, et al. Impact of self-heating effects on nanoscale Ge p-channel FinFETs with Si substrate. Sci China Inf Sci, 2018, 61: 062401
Pop E, Sinha S, Goodson K E. Heat generation and transport in nanometer-scale transistors. Proc IEEE, 2006, 94: 1587–1601
He P, Lin X, Jiang B, et al. Measurement and simulation of electrical and thermal property of drain and source on insulator MOSFETs (DSOI). In: Proceedings of IEEE International SOI Conference, Williamsburg, 2002. 55–57
Narayanan M R, Nashash H A. Minimization of selfheating in SOI MOSFET devices with SELBOX structure. In: Proceedings of International Conference on Advanced Semiconductor Devices & Microsystems, Smolenice, 2016. 61–64
Acknowledgements
This work was supported by National Science and Technology Major Project (Grant No. 2016ZX02301003), National Natural Science Foundation of China (Grant Nos. 61574056, 61704056), Shanghai Sailing Program (Grant No. YF1404700), and Science and Technology Commission of Shanghai Municipality (Grant No. 14DZ2260800).
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Huang, Q., Liu, R., Sun, Y. et al. Physical mechanism of performance adjustment in selective buried oxide n-MOSFETs. Sci. China Inf. Sci. 62, 69407 (2019). https://doi.org/10.1007/s11432-018-9791-2
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DOI: https://doi.org/10.1007/s11432-018-9791-2