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Nano-scaled transistor reliability characterization at nano-second regime

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References

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Acknowledgements

This work was partly supported by the National Major Science and Technology Special Project of China (Grant No. 2017ZX02301007-001), National Natural Science Foundation of China (Grant No. 61704152), and Zhejiang Provincial Natural Science Foundation of China (Grant No. LY19F040008). The authors gratefully acknowledge Dr. Q. LUO from Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China, for inspiring discussion.

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Authors and Affiliations

  1. School of Micro-Nano Electronics, Zhejiang University, Hangzhou, 311200, China

    Ran Cheng, Ying Sun & Bing Chen

  2. College of Electronic Engineering and Information Science, Zhejiang University, Hangzhou, 310027, China

    Yiming Qu & Wei Liu

  3. Institute of Microelectronics, Chinese Academy of Sciences, Beijing, 100029, China

    Fanyu Liu & Jianfeng Gao

  4. Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, 94720, USA

    Nuo Xu

Authors
  1. Ran Cheng
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  2. Ying Sun
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  3. Yiming Qu
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  4. Wei Liu
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  5. Fanyu Liu
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  6. Jianfeng Gao
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  7. Nuo Xu
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  8. Bing Chen
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Correspondence to Bing Chen.

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Cheng, R., Sun, Y., Qu, Y. et al. Nano-scaled transistor reliability characterization at nano-second regime. Sci. China Inf. Sci. 64, 209401 (2021). https://doi.org/10.1007/s11432-020-3088-3

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  • DOI: https://doi.org/10.1007/s11432-020-3088-3

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