Abstract
A wide variety of real-time applications (e.g. multimedia, communication, etc.) require implementations that meet tight timing constraints. This work introduces novel high-performance FPGA architecture capable of implementing efficiently any time critical application. The fundamental contribution of the proposed reconfigurable architecture is the design of a highly efficient (performance and power consumption) interconnection structure, taking into consideration the statistical and spatial data extracted from applications, which are implemented on Virtex FPGAs. The derived architecture is software-supported by the MEANDER design framework. Using a number of real-time applications, extensive comparison study in terms of several design parameters proves the effectiveness of the proposed architecture against to Virtex one. More specifically, the proposed architecture achieves performance improvement and power savings up to 20 and 16%, respectively. Moreover, compared to a Virtex architecture with same power budget, our architecture achieves performance improvement by 42%.
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Acknowledgments
This paper is part of the 03ED593 research project, implemented within the framework of the “Reinforcement Program of Human Research Manpower” (PENED) and co-financed by National and Community Funds (75% from E.U.-European Social Fund and 25% from the Greek Ministry of Development-General Secretariat of Research and Technology).
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Siozios, K., Soudris, D. Designing a novel high-performance FPGA architecture for data intensive applications. J Real-Time Image Proc 4, 155–166 (2009). https://doi.org/10.1007/s11554-008-0099-4
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DOI: https://doi.org/10.1007/s11554-008-0099-4