Skip to main content
SpringerLink
Log in

A reduced memory bandwidth and high throughput HDTV motion compensation decoder for H.264/AVC High 4:2:2 profile

  • Special Issue
  • Published:
Journal of Real-Time Image Processing Aims and scope Submit manuscript

Abstract

This article presents the HP422-MoCHA: optimized Motion Compensation hardware architecture for the High 4:2:2 profile of H.264/AVC video coding standard. The proposed design focuses on real-time decoding for HDTV 1080p (1,920 × 1,080 pixels) at 30 fps. It supports multiple sample bit-width (8, 9, or 10 bits) and multiple chroma sub-sampling formats (4:0:0, 4:2:0, and 4:2:2) to provide enhanced video quality experience. The architecture includes an optimized sample interpolator that processes luma and chroma samples in two parallel datapaths and features quarter sample accuracy, bi-prediction and weighted prediction. HP422-MoCHA also includes a hardwired Motion Vector Predictor, supporting temporal and spatial direct predictions. A novel memory hierarchy implemented as a 3-D Cache reduces the frame memory access, providing, on average, 62% of bandwidth and 80% of clock cycles reduction. The design was implemented in a Xilinx Virtex-II PRO FPGA, and also in an ASIC with a TSMC 0.18 μm standard cells technology. The ASIC implementation occupies 102 K equivalent gates and 56.5 KB of on-chip SRAM in a 3.8 × 3.4 mm2 area. It presents a power consumption of 130 mW. Both implementations reach a maximum operation frequency of ~100 MHz, being able to motion compensate 37 bi-predictive frames or 69 predictive fps. The minimum required frequency to ensure the real-time decoding for HD1080p at 30 fps is 82 MHz. Since HP422-MoCHA is the first Motion Compensation architecture for the High 4:2:2 profile found in the literature, a Main profile MoCHA was used for comparison purposes, showing the highest throughput among all presented works. However, the HP422-MoCHA architecture also reaches the highest throughput when compared with the other published Main profile MC solutions, even considering the significantly higher complexity of the High 4:2:2 profile.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10

Similar content being viewed by others

References

  1. Wiegand, T., Sullivan, G., Luthra, A. (JVT eds), Draft ITU-T recommendation and final draft international standard of joint video specification (ITU-T Rec.H.264 ISO/IEC 14496-10 AVC), JVT-G050r1, Geneva (2003)

  2. ITU-T Recommendation H.264/AVC (03/09): advanced video coding for generic audiovisual services (2009)

  3. Brazilian Forum of Digital Television. ISDTV Standard. Draft (2006) (in portuguese)

  4. Sullivan, G.J., Wiegand, T.: Video compression—from concepts to the H.264/AVC standard. In: Proceedings of the IEEE, vol. 93, no. 1, pp. 18–31 (2005)

  5. Zhou, X., Li, E.Q., Chen, Y.-K.: Implementation of H.264 decoder on general-purpose processors with media instructions. In: SPIE Conference on Image and Video Communications and Processing (2003)

  6. Chen, J.-W., Lin, C.-C., Guo, J.-I., Wang, J.-S.: Low complexity architecture design of H.264 predictive pixel compensator for HDTV application, acoustics, speech and signal processing, 2006. In: ICASSP 2006 Proceedings. 2006 IEEE International Conference, vol. 3, pp. 932–935 May 2006

  7. Wang, R., Li, M., Li, J., Zhang, Y., et al.: High throughput and low memory access sub-pixel interpolation architecture for H.264/AVC HDTV decoder. IEEE Trans Consumer Electron 51(3), 1006–1013 (2005)

    Article  Google Scholar 

  8. Wang, S.-Z., Lin, T.-M., Liu, Lee, C.-Y., et al.: A new motion compensation design for H.264/AVC decoder. IEEE Int Symposium Circuits Syst ISCAS 5, 4558–4561 (2005)

    Google Scholar 

  9. Lie, W.-N., Yeh, H.-C., Lin, T.C.-I., Chen, C.-F., et al.: Hardware-efficient computing architecture for motion compensation interpolation in H.264 video coding. IEEE Int Symposium Circuits Syst (ISCAS) 3(23–26), 2136–2139 (2005)

    Google Scholar 

  10. Azevedo, A., Zatt, B., Agostini, L., Bampi, S.: MoCHA: a bi-predictive motion compensation hardware for H.264/AVC decoder targeting HDTV. In: IEEE ISCAS (2007)

  11. Zatt, B., Susin, A., Bampi, S., Agostini, L.: HP422-MoCHA: a H.264/AVC High profile motion compensation architecture for HDTV. IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008, pp. 25–28, 18–21 May 2008

  12. Wang, R., Li, J., Huang, C.: Motion compensation memory access optimization strategies for H.264/AVC decoder. In: Proceedings (ICASSP ’05) IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005 vol. 5, no., pp. v/97–v100 vol. 5, 18–23 March 2005

  13. Zatt, B., Azevedo, A., Agostini, L., Susin, A., Bampi, S.: Memory hierarchy targeting bi-predictive motion compensation for H.264/AVC decoder. ISVLSI ’07. IEEE Computer Society Annual Symposium on VLSI, pp. 445–446, 9–11 March 2007

  14. http://www.xilinx.com. Accessed 10 May 2010

  15. http://www.simplicity.com. Accessed 10 May 2010

  16. http://iphome.hhi.de/suehring/tml. Accessed 10 May 2010

  17. http://www.mentor.com/products/fv/modelsim/. Accessed 10 May 2010

  18. Artisan components, TSMC 0.18 mm process 1.8-Volt SAGE-X™ standard cell library, Release 4.1, Set. 2003

  19. http://www.cadence.com. Accessed 10 May 2010

  20. http://www.arm.com/products/physicalip/. Accessed 10 May 2010

  21. Wilton, S.J.E., Jouppi, N.P.: CACTI: an enhanced cache access and cycle time model. IEEE J Solid-State Circuits 31(5), 677–688 (1996)

    Article  Google Scholar 

  22. Finchelstein, D.F., Sze, V., Sinangil, M.E., Koken, Y., Chandrakasan, A.P.: A low-power 0.7-V H.264 720p video decoder. Solid-State Circuits Conference, 2008. A-SSCC ’08. IEEE Asian, pp. 173–176, 3–5 Nov 2008

  23. Li, Y., He, Y.: Bandwidth optimized and high performance interpolation architecture in motion compensation for H.264/AVC HDTV decoder. J Signal Process Syst 52(2), 111–126 (2008)

    Article  Google Scholar 

  24. Ma, L. et al.: Fractional-pel motion compensation interpolation architecture based on parallel FIR systolic arrays for H.264/AVC. ASID 2008. 2nd International Conference on Anti-counterfeiting, Security and Identification, 2008, vol., no., pp. 328–331, 20–23 Aug 2008

  25. Xu, K., Choy, C.-S.: A power-efficient and self-adaptive prediction engine for H.264/AVC decoding. IEEE Trans Very Large Scale Integr (VLSI) Syst 16(3), 302–313 (2008)

    Article  Google Scholar 

  26. Zheng, J., Gao, W., Wu, D., Xie, D., et al.: A novel VLSI architecture of motion compensation for multiple standards. IEEE Trans Consumer Electron 54(2), 687–694 (2008)

    Article  Google Scholar 

  27. Chuang, T.-D., Chang, L.-M., Chiu, T.-W., Chen, Y.-H., Chen, L.-G.: Bandwidth-efficient cache-based motion compensation architecture with DRAM-friendly data access control. ICASSP 2009. IEEE International Conference on Acoustics, Speech and Signal Processing, 2009, pp. 2009–2012, 19–24 April 2009

  28. Saponara, S., Denolf, K., Lafruit, G., et al.: Performance and complexity co-evaluation of the advanced video coding standard for cost-effective multimedia communications. EURASIP J Appl Signal Process 2004(2), 220–235 (2004)

    Article  Google Scholar 

  29. Zatt, B., Agostini, L., Susin, A., Bampi, S.: High throughput architecture for H.264/AVC motion compensation sample interpolator for HDTV. SBCCI ’08. 21st Annual Symposium on Integrated Circuits and System Design, pp. 228–232, 1–4 Sep 2008

  30. Marpe, D., Wiegand, T., Sullivan, G., et al.: The H.264/MPEG4 advanced video coding standard and its applications. IEEE Commun Mag 44(8), 134–143 (2006)

    Article  Google Scholar 

  31. Marpe, D., Wiegand, T., Gordon, S.: H.264/MPEG4-AVC fidelity range extensions: tools, profiles, performance, and application areas. ICIP ’05. IEEE International Conference on Image Processing, pp. I-593–6, 14 Nov 2005

Download references

Author information

Authors and Affiliations

  1. Informatics Institute, Microelectronics Groups (GME), PGMICRO, Federal University of Rio Grande do Sul, UFRGS, Porto Alegre, Brazil

    Bruno Zatt, Leandro M. de L. Silva & Sergio Bampi

  2. Electrical Engineering Department, PPGEE & PPGC, Federal University of Rio Grande do Sul, UFRGS, Porto Alegre, Brazil

    Altamiro Susin

  3. Faculty of Electrical Engineering, Mathematics and Computer Science, Delft University of Technology, Delft, Netherlands

    Arnaldo Azevedo

  4. Group of Architectures and Integrated Circuits, GACI, Federal University of Pelotas, UFPel, Pelotas, Brazil

    Luciano Agostini

Authors
  1. Bruno Zatt
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Leandro M. de L. Silva
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Arnaldo Azevedo
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Luciano Agostini
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Altamiro Susin
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Sergio Bampi
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Bruno Zatt.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Zatt, B., de L. Silva, L.M., Azevedo, A. et al. A reduced memory bandwidth and high throughput HDTV motion compensation decoder for H.264/AVC High 4:2:2 profile. J Real-Time Image Proc 8, 127–140 (2013). https://doi.org/10.1007/s11554-011-0216-7

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11554-011-0216-7

Keywords

Search

Navigation