Skip to main content
SpringerLink
Log in

Embedded architecture for noise-adaptive video object detection using parameter-compressed background modeling

  • Original Research Paper
  • Published:
Journal of Real-Time Image Processing Aims and scope Submit manuscript

Abstract

Video processing algorithms are computationally intensive and place stringent requirements on performance and efficiency of memory bandwidth and capacity. As such, efficient hardware accelerations are inevitable for fast video processing systems. In this paper, we propose resource- and power-optimized FPGA-based configurable architecture for video object detection by integrating noise estimation, Mixture-of-Gaussian background modeling, motion detection, and thresholding. Due to large amount of background modeling parameters, we propose a novel Gaussian parameter compression technique suitable for resource- and power-constraint embedded video systems. The proposed architecture is simulated, synthesized and verified for its functionality, accuracy and performance on a Virtex-5 FPGA-based embedded platform by directly interfacing to a digital video input. Intentional exploitation of heterogeneous resources in FPGAs, and advanced design techniques such as heavy pipelining and data parallelism yield real-time processing of HD-1080p video streams at 30 frames per second. Objective and subjective evaluations to existing hardware-based methods show that the proposed architecture obtains orders of magnitude performance improvements, while utilizing minimal hardware resources. This work is an early attempt to devise a complete video surveillance system onto a stand-alone resource-constraint FPGA-based smart camera.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19
Fig. 20
Fig. 21
Fig. 22
Fig. 23
Fig. 24
Fig. 25

Similar content being viewed by others

References

  1. Oliver, N., Rosario, B., Pentland, A.: A Bayesian computer vision system for modeling human interactions. IEEE Trans. Pattern Anal. Mach. Intell. 22(8), 831–843 (2000)

    Article  Google Scholar 

  2. Li, L., Huang, W., Gu, I.Y.H., Tian, Q.: Statistical modeling of complex backgrounds for foreground object detection. IEEE Trans Image Process. 13(11), 1459–1472 (2004)

    Article  Google Scholar 

  3. Cheung, S.C.S., Kamath, C.: Robust techniques for background subtraction in urban traffic video. Proc. SPIE 5308, 881–892 (2004)

    Article  Google Scholar 

  4. Happe, M., Lübbers, E., Platzner, M.: A self-adaptive heterogeneous multi-core architecture for embedded real-time video object tracking. J. Real Time Image Process. (2011) (Published online)

  5. Chakraborty, D., Shankar, B.U., Pal, S.K.: Granulation, Rough Entropy and Spatiotemporal Moving Object Detection. Applied Soft Computing (2012)

  6. Gao, H., Peng, Y., Dai, Z., Xie, F.: A new detection algorithm of moving objects based on human morphology. In: IEEE International Conference on Intelligent Information Hiding and Multimedia, Signal Processing, pp. 411–414 (2012)

  7. Wang, Y.T., Chen, K.W., Chiou, M.J.: Moving object detection using monocular vision. Intell. Auton. Syst., pp. 183–192 (2013)

  8. Stauffer, C., Grimson, W.E.: Learning patterns of activity using real-time tracking. IEEE Trans. Pattern Anal. Mach. Intell. 22(8), 747–757 (2000)

    Article  Google Scholar 

  9. Piccardi, M.: Background subtraction techniques: a review. IEEE Int. Conf. Syst. Man Cybern. 4, 3099–3104 (2004)

    Google Scholar 

  10. Cope, B., Cheung, P.Y.K., Luk, W., Howes, L.: Performance comparison of graphics processors to reconfigurable logic: a case study. IEEE Trans. Comput. 59(4), 433–448 (2010)

    Article  MathSciNet  Google Scholar 

  11. Papakonstantinou, A., Gururaj, K., Stratton, J.A., Chen, D., Cong, J., Hwu, W.M.W.: FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs. In: IEEE Symposium on Application Specific Processors, pp. 35–42 (2009)

  12. Amer, A., Dubois, E.: Fast and reliable structure-oriented video noise estimation. IEEE Trans. Circuits Syst. Video Technol. 15, 113–118 (2005)

    Article  Google Scholar 

  13. Achkar, F., Amer, A.: Hysteresis-based selective Gaussian mixture models for real-time background maintenance. IS T/SPIE Symp. Electron. Imaging 6508(2), 65082J.1–65082J.11 (2007)

  14. Amer, A.: Memory-based spatio-temporal real-time object segmentation. In: SPIE International Symposium on Electronic Imaging, Conference on Real-Time Imaging, vol. 5012, pp. 10–21 (2003)

  15. Ratnayake, K., Amer, A.: An FPGA-based implementation of spatio-temporal object segmentation. In: IEEE International Conference on Image Processing, pp. 3265–3268 (2006)

  16. Zhang, D., Lu, G.: Segmentation of moving objects in image sequence: a review. Circuits Syst. Signal Process. 20(2), 143–183 (2001)

    Article  MATH  Google Scholar 

  17. Karman, K.P., von Brandt, A.: Moving object recognition using an adaptive background memory. Time Varying Image Process. Movi. Object Recogn., pp. 297–307 (1990)

  18. Toyama, K., Krumm, J., Brumitt, B., Meyers, B.: Wallflower: Principles and practice of background maintenance. IEEE Int. Conf. Comput. Vis. 1, 255–261 (1999)

    Google Scholar 

  19. Zivkovic, Z.: Improved adaptive Gaussian mixture model for background subtraction. In: IEEE International Conference on the, Pattern Recognition, pp. 28–31 (2004)

  20. Lee, D.S.: Effective Gaussian mixture learning for video background subtraction. IEEE Trans. Pattern Anal. Mach. Intell. 27(5), 827–832 (2005)

    Article  Google Scholar 

  21. Cucchiara, R., Grana, C., Piccardi, M., Prati, A.: Detecting moving objects, ghosts, and shadows in video streams. IEEE Trans. Pattern Anal. Mach. Intell. 25(10), 1337–1342 (2003)

    Article  Google Scholar 

  22. Elgammal, A.M., Duraiswami, R., Davis, L.S.: Efficient kernel density estimation using the fast gauss transform with applications to color modeling and tracking. IEEE Trans. Pattern Anal. Mach. Intell. 25(11), 1499–1504 (2003)

    Article  Google Scholar 

  23. Appiah, K., Hunter, A.: A Single-Chip FPGA implementation of real-time adaptive background model. In: EEE International Conference on Field-Programmable Technolog, pp. 95–102 (2005)

  24. Oliveira, J., Printes, A., Freire, R.C.S., Melcher, E., Silva, I.S.S.: FPGA architecture for static background subtraction in real time. In: Annual Symposium on Integrated Circuits and Systems Design, pp. 26–31 (2006)

  25. Schlessman, J., Lodato, M., Ozer, B., Wolf, W.: Heterogeneous MPSoC architectures for embedded computer vision. In IEEE International Conference on Multimedia and Expo, pp. 1870–1873 (2007)

  26. Kristensen, F., Hedberg, H., Jiang, H., Nilsson, P., Öwall, V.: An embedded real-time surveillance system: implementation and evaluation. J. Signal Process. Syst. 52(1), 75–94 (2008)

    Article  Google Scholar 

  27. Jiang, H., Ardo, H., Öwall, V.: A hardware architecture for real-time video segmentation utilizing memory reduction techniques. IEEE Trans. Circuits Syst. Video Technol. 19(2), 226–236 (2009)

    Article  Google Scholar 

  28. Genovese, M., Napoli, E.: FPGA-based architecture for real time segmentation and denoising of HD video. J. Real Time Image Process. (2011) (Published online)

  29. Teuhola, J.: A compression method for clustered bit-vectors. Inf. Process. Lett. 7, 308–311 (1978)

    Article  MATH  Google Scholar 

  30. Ratnayake, K., Amer, A.: An FPGA architecture of stable-sorting on a large data volume: application to video signals. In: IEEE Conference on Information Sciences and Systems, pp. 431–436 (2007)

  31. Wang, T.C., Fang, H.C., Chao, W.M., Chen, H.H., Chen, L.G.: An UVLC encoder architecture for H. 26L. In: IEEE International Symposium on Circuits and Systems, vol. 2, pp. 308–311 (2002)

  32. Osman, H., Mahjoup, W., Nabih, A., Aly, G.M.: JPEG encoder for low-cost FPGAs. In: International Conference on Computer Engineering Systems, pp. 406–411 (2007)

  33. Yu, G., Vladimirova, T., Wu, X., Sweeting, M.N.: A new high-level reconfigurable lossless image compression system for space applications. In: NASA/ESA Conference on Adaptive Hardware and Systems, pp. 183–190 (2008)

  34. Mahapatra, S., Singh, K.: An FPGA-based implementation of multi-alphabet arithmetic coding. IEEE Trans. Circuits Syst. I Regul. Papers 54(8), 1678–1686 (2007)

    Article  Google Scholar 

  35. Rosin, P.L.: Thresholding for change detection. Comput. Vis. Image Underst. 86, 79–95 (2002)

    Article  MATH  Google Scholar 

Download references

Acknowledgments

This work was supported, in part, by the Fonds de la recherche sur la nature et les technologies du Quebec (NATEQ).

Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Concordia University, Montréal, QC, Canada

    Kumara Ratnayake & Aishy Amer

Authors
  1. Kumara Ratnayake
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Aishy Amer
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Kumara Ratnayake.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Ratnayake, K., Amer, A. Embedded architecture for noise-adaptive video object detection using parameter-compressed background modeling. J Real-Time Image Proc 13, 397–414 (2017). https://doi.org/10.1007/s11554-014-0418-x

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11554-014-0418-x

Keywords

Search

Navigation