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Efficient DVFS for low power HEVC software decoder

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Abstract

Low power design is a primary concern for modern battery-driven devices and video applications such as video decoding are often the most resource intensive applications of consumer electronics devices. Modern embedded processors are now proven to support video applications with software. They are also equipped with advanced features including Dynamic Voltage Frequency Scaling and Dynamic Power Management in order to reduce their power consumption. High Efficiency Video Coding (HEVC) is the latest MPEG video standard offering state-of-the-art compression rates and advanced parallel processing solutions. This paper presents a low power real-time software architecture for a HEVC decoder. Software decoding fosters short time-to-market as it relies on software designs for a general purpose processor. The proposed architecture exploits the characteristics of the multicore ARM big.LITTLE System-on-a-Chip to provide a low power design. Extensive power measurements as well as real-time metrics are provided to compare the proposed architecture with state-of-the-art.

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Notes

  1. Optimized software refers in this paper to a code-source written with Single Instruction Multiple Data (SIMD) operations.

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Acknowledgments

This work is partially supported by BPI France, Region Ile-de-France, Region Bretagne and Rennes Metropole through the GreenVideo Project.

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Authors and Affiliations

  1. IETR, UMR CNRS 6164, UEB, INSA Rennes, 20 Avenue des Buttes de Coesmes, 35708, Rennes, France

    Erwan Nogues, Julien Heulot, Glenn Herrou, Ladislas Robin, Maxime Pelcat, Daniel Menard, Erwan Raffin & Wassim Hamidouche

  2. Institut Pascal, UMR CNRS 6602, Campus Universitaire des Cézeaux, 4 Impasse Blaise Pascal, 63178, Aubière, France

    Maxime Pelcat

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  1. Erwan Nogues
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  2. Julien Heulot
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Correspondence to Erwan Nogues.

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Nogues, E., Heulot, J., Herrou, G. et al. Efficient DVFS for low power HEVC software decoder. J Real-Time Image Proc 13, 39–54 (2017). https://doi.org/10.1007/s11554-016-0624-9

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  • DOI: https://doi.org/10.1007/s11554-016-0624-9

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