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Compiler-directed power optimization of high-performance interconnection networks for load-balancing MPI applications

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Abstract

Energy consumption of parallel computers has been becoming the obstruction to higher-performance systems. In this paper, we focus on power optimization of high-performance interconnection networks for MPI applications in high-performance parallel computers. Compared with the past history-based work, we propose the idea of compiler-directed power-aware on/off network links. There are some idle intervals for network links during the execution of parallel applications, at which the links still consume large amounts of energy. Using on/off network links, compiler first divides load-balancing MPI applications into the communication intervals and the computation intervals, and then inserts the on/off instruction into the applications to switch the link state. To avoid the time overhead of state switching, we use a time estimation technique to analyze the computation time, and insert the on instruction before reaching the communication intervals. Results from simulations and experiments show that the proposed compiler-directed method can reduce energy consumption of interconnection networks by 20∼70%, at a loss of less than 1% network latency and performance degradation.

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Authors and Affiliations

  1. School of Computer, National University of Defense Technology, Changsha, 410073, China

    Yang Xuejun, Yi Huizhan, Qu Xiangli & Zhou Haifang

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  1. Yang Xuejun
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  2. Yi Huizhan
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  3. Qu Xiangli
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  4. Zhou Haifang
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Correspondence to Yi Huizhan.

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Yang, X., Yi, H., Qu, X. et al. Compiler-directed power optimization of high-performance interconnection networks for load-balancing MPI applications. Front. Comput. Sc. China 1, 94–105 (2007). https://doi.org/10.1007/s11704-007-0008-1

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  • DOI: https://doi.org/10.1007/s11704-007-0008-1

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