Skip to main content
SpringerLink
Log in

Exploiting write power asymmetry to improve phase change memory system performance

  • Research Article
  • Published:
Frontiers of Computer Science Aims and scope Submit manuscript

Abstract

Phase change memory (PCM) is a promising candidate to replace DRAM as main memory, thanks to its better scalability and lower static power than DRAM. However, PCM also presents a few drawbacks, such as long write latency and high write power. Moreover, the write commands parallelism of PCM is restricted by instantaneous power constraints, which degrades write bandwidth and overall performance. The write power of PCM is asymmetric: writing a zero consumes more power than writing a one. In this paper, we propose a new scheduling policy, write power asymmetry scheduling (WPAS), that exploits the asymmetry of write power. WPAS improveswrite commands parallelism of PCM memory without violating power constraint. The evaluation results show that WPAS can improve performance by up to 35.5%, and 18.5% on average. The effective read latency can be reduced by up to 33.0%, and 17.1% on average.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Lefurgy C, Rajamani K, Rawson F, Felter W, Kistler M, Keller T W. Energy management for commercial servers. IEEE Computer, 2003, 36(12): 39–48

    Article  Google Scholar 

  2. Lim K, Ranganathan P, Chang J, Patel C, Mudge T, Reinhardt S. Understanding and designing new server architectures for emerging warehouse-computing environments. In: Proceedings of 35th International Symposium on Computer Architecture. 2008, 315–326

    Google Scholar 

  3. Udipi A N, Muralimanohar N C, Niladrish B, Rajeev D, Al J, Norman P. Rethinking DRAM design and organization for energy-constrained multi-cores. SIGARCH Computer Architecture News, 2010, 38(3): 175–186

    Article  Google Scholar 

  4. Lee B C, Ipek E, Mutlu O, Burger D. Architecting phase change memory as a scalable dram alternative. SIGARCH Computer Architecture News, 2009, 37(3): 2–13

    Article  MATH  Google Scholar 

  5. Hay A, Strauss K, Sherwood T, Loh G H, Burger D. Preventing PCM banks from seizing too much power. In: Proceedings of the 44th Annual International Symposium on Microarchitecture. 2011, 186–195

    Google Scholar 

  6. Yue J, Zhu Y. Exploiting subarrays inside a bank to improve phase change memory performance. In: Proceedings of Design, Automation Test in Europe Conference Exhibition. 2013, 386–391

    Google Scholar 

  7. Ni J, Hu W, Li G, Tan K, Sun D. Bp-tree: a predictive B+-tree for reducing writes on phase change memory. IEEE Transaction on Knowledge and Data Engineering, 2014, 26(10): 2368–2381

    Article  Google Scholar 

  8. Qureshi M K, Franceschini M M, Jagmohan A, Lastras L A. PreSET: improving performance of phase change memories by exploiting asymmetry in write times. In: Proceedings of the 39th Annual International Symposium on Computer Architecture. 2012, 380–391

    Google Scholar 

  9. Yang B, Lee D, Kim J, Cho J, Lee J, Yu S Y, Gon B. A low power phase-change random access memory using a data-comparison write scheme. In: Proceedings of International Symposium on Circuits and Systems. 2007, 3014–3017

    Google Scholar 

  10. Yamada N O, Eiji N, Kenichi A. Nobuo T, Masatoshi. Rapid phase transitions of GeTeSb2Te3 pseudobinary amorphous thin films for an optical disk memory. Journal of Applied Physics, 1991, 69(5): 2849–2856

    Article  Google Scholar 

  11. Kang S, Cho W Y, Cho B H, Lee K J, Lee C S. Oh H R, Choi B G, Wang Q, Kim H J, Park M H, Ro Y H, Kim S, Kim D E, Cho K S, Ha C D, Kim Y R, Kim K S, Hwang C R, Kwak C K, Byun H G, Shin Y S. A 0.1/spl mu/m 1.8V 256Mb 66MHz synchronous burst PRAM. In: Proceedings of International Conference on Solid-State Circuits- Digest of Technical Papers. 2006, 487–496

    Google Scholar 

  12. On H, Cho B H, Cho W Y. Enhanced write performance of a 64 Mb phase-change random access memory. In: Proceedings of International Conference on Solid-State Circuits-Digest of Technical Papers. 2005, 581–584

    Google Scholar 

  13. Lee Y, Kim S, Hong S, Lee J. Skinflint DRAM system: minimizing DRAM chip writes for low power. In: Proceedings of the 17th International Symposium on High Performance Computer Architecture. 2013, 25–34

    Google Scholar 

  14. Muralimanohar N, Balasubramonian R, Jouppi N P. CACTI 6.0: a tool to model large caches. HP Laboratories, 2009, 22–31

    Google Scholar 

  15. Bruce J, Spencer W, Wang D. Memory systems-cache, DRAM, disk. Morgan Kaufmann. 2008, 428–429

    Google Scholar 

  16. Binkert N, Beckmann B, Black G, Reinhardt S K, Saidi A, Basu A, Hestness J, Hower D R, Krishna T, Sardashtis, Sen R, Sewell K, Shoaib M, Vaish N, Hill M D, Wood D A. The gem5 simulator. SIGARCH Computer Architecture News, 2011, 39(2): 1–7

    Article  Google Scholar 

  17. Rosenfeld P, Cooper B E, Jacob B. DRAMSim2: a cycle accurate memory system simulator. Computer Architecture Letters, 2011, 10(1): 16–19

    Article  Google Scholar 

  18. Standard Performance Evaluation Corporation. SPEC CPU 2006.

  19. Zheng H, Lin J, Zhang Z, Gorbatov E, David H, Zhu Z. Mini-rank: adaptive DRAM architecture for improving memory power efficiency. In: Proceedings of the 41st International Symposium on Microarchitecture. 2008, 210–221

    Google Scholar 

  20. Ahn J H, Leverich J, Schreiber R S, Jouppi N P. Multicore DIMM: an energy efficient memory module with independently controlled DRAMs. Computer Architecture Letters, 2009, 8(1): 5–8

    Article  Google Scholar 

  21. Cho S, Lee H. Flip-N-Write: a simple deterministic technique to im prove PRAM write performance, energy and endurance. In: Proceedings of the 42nd Annual International Symposium on Microarchitecture. 2009, 347–357

    Google Scholar 

  22. Qureshi M K, Srinivasan V, Rivers J A. Scalable high performance main memory system using phase-change memory technology. In: Proceedings of the 36th Annual International Symposium on Computer Architecture. 2009, 24–33

    Google Scholar 

  23. Ramos L E, Gorbatov E, Bianchini R. Page placement in hybrid memory systems. In: Proceedings of International Conference on Supercomputing. 2011, 85–95

    Google Scholar 

  24. Lee S, Bahn H, Noh S H. Characterizing memory write references for efficient management of hybrid PCM and DRAM memory. In: Proceedings of the 19th International Symposium on Modeling, Analysis Simulation of Computer and Telecommunication Systems. 2011, 168–175

    Google Scholar 

  25. Lee H G, Baek S, Nicopoulos C, Kim J. An energy- and performanceaware DRAM cache architecture for hybrid DRAM/PCM main memory systems. In: Proceedings of the 29th International Conference on Computer Design. 2011, 381–387

    Google Scholar 

  26. Jiang L, Zhang Y, Childers B R, Yang J. FPB: fine-grained power budgeting to improve write throughput of multi-level cell phase change memory. In: Proceedings of the 45th Annual IEEE/ACM International Symposium. on Microarchitecture. 2012, 1–12

    Google Scholar 

  27. Li Z, Zhou R, Li T. Exploring high-performance and energy proportional interface for phase change memory systems. In: Proceedings of the 17th International Symposium on High Performance Computer Architecture. 2013, 210–221

    Google Scholar 

  28. Ham B K, Chelepalli T J, Lee N, Xue B C. Disintegrated control for energy-efficient and heterogeneous memory systems. In: Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture. 2013, 424–435

    Google Scholar 

  29. Chen J, Chiang R C, Huang H H, Venkataramani G. Energy-aware writes to non-volatile main memory. ACM SIGOPS Operating Systems Review, 2012, 5(3): 48–52

    Article  Google Scholar 

  30. Yue J, Zhu Y. Accelerating write by exploiting PCM asymmetries. In: Proceedings of the 17th International Symposium on High Performance Computer Architecture. 2013, 282–293

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Institute of Acoustics, Chinese Academy of Sciences, Beijing, 100190, China

    Qi Wang, Donghui Wang & Chaohuan Hou

  2. School of Physics, University of Chinese Academy of Sciences, Beijing, 100049, China

    Qi Wang

Authors
  1. Qi Wang
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Donghui Wang
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Chaohuan Hou
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Qi Wang.

Additional information

QiWang is a PhD candidate in Institute of Acoustics, Chinese Academy of Sciences, China. Her research interests include VLSI design, computer architecture, and emerging memory technologies.

Donghui Wang received his BS from Tsinghua University, China in 1997. He received the PhD from Institute of Semiconductors, Chinese Academy of Sciences in 2002. Now, he is a professor of Institute of Acoustics, Chinese Academy of Sciences. His research interests include digital signal processor design, VLSI design and signal processing.

Chaohuan Hou received his BS from Peking University, China in 1958. He is a professor of Institute of Acoustics, Chinese Academy of Sciences, China. He was elected as a member of the Academic Division of Science and Technology, the Chinese Academy of Sciences in 1995. His research interests include VLSI signal processing, DSP design, and CPU design.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Wang, Q., Wang, D. & Hou, C. Exploiting write power asymmetry to improve phase change memory system performance. Front. Comput. Sci. 9, 566–575 (2015). https://doi.org/10.1007/s11704-014-4185-4

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11704-014-4185-4

Keywords

Search

Navigation