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A novel method for high-level synthesis of datapaths in digital filters using a moth-flame optimization algorithm

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Abstract

High-level synthesis (HLS) is one of the most important processes in digital VLSI circuit design. Owing to complexity and enormity of the design space in HLS problems, employing meta-heuristic methods and swarm intelligence has been considered as a highly favorable option when solving such problems. This research work proposes a moth-flame optimization (MFO) algorithm-based method for HLS of datapaths in digital filters, where scheduling, allocating, and binding steps were performed simultaneously. It was observed that the efficiency of the proposed method enjoyed an improved efficiency thanks to the mentioned simultaneous steps while being combined with the MFO algorithm. By comparing the performance of the proposed method with Genetic algorithm based method and particle swarm optimization based method for HLS of digital filters benchmarks, it can be inferred that the proposed method outperforms the other two methods in HLS of digital filters. This is evidently approved by a maximum improvement observed in the rates of the delay, the occupied area of the chip, and the power consumption for 2.99%, 6.58%, and 6.48%, respectively. In addition to the mentioned improvement, another striking characteristic of the proposed method is its fast runtime in reaching a response. This could significantly lower the costs while increasing the design speed of circuits having large dimensions. As well, an averagely 20% rise was also discerned in the algorithm runtime compared to the other two methods.

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References

  1. Kim NS, Xiong J, Hwu WW (2017) heterogeneous computing meets near-memory acceleration and high-level synthesis in the post-moore era. IEEE Micro 37(4):10–18

    Article  Google Scholar 

  2. Pilato C, Garg S, Wu K, Karri R, Regazzoni F (2018) Securing hardware accelerators: a new challenge for high-level synthesis. IEEE Embed Syst Lett 10(3):77–80

    Article  Google Scholar 

  3. Sengupta A, Bhadauria S, Mohanty SP (2017) TL-HLS: methodology for low cost hardware trojan security aware scheduling with optimal loop unrolling factor during high level synthesis. IEEE Trans Comput Aided Des Integr Circuits Syst 36(4):655–668

    Article  Google Scholar 

  4. Mahapatra A, Schafer BC (2019) VeriIntel2C: abstracting RTL to C maximize high-level synthesis design space exploration. Integration 64:1–12

    Article  Google Scholar 

  5. Das S, Maity R, Maity NP (2018) VLSI-based pipeline architecture for reversible image watermarking by difference expansion with high-level synthesis approach. Circuits Syst Signal Process 37(4):1575–1593

    Article  MathSciNet  Google Scholar 

  6. Zhao J, Feng L, Sinha S, Zhang W, Liang Y, He B (2017) COMBA: a comprehensive model-based analysis framework for high level synthesis of real applications In: Proceedings IEEE/ACM international conference on computer-aided design, Irvine

  7. Fezzardi P, Pilato C, Ferrandi F (2018) Enabling automated bug detection for IP-based design using high-level synthesis. IEEE Des Test 35(5):54–62

    Article  Google Scholar 

  8. Tang X, Jiang T, Jones A, Banerjee P (2005) Behavioral synthesis of data-dominated circuits for minimal energy implementation In: Proceedings of 18th the international conference on VLSI design, 3–7 Jan. 2005

  9. Chabini N, Wolf W (2005) Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints. IEEE Trans VLSI Syst 13(10):1113–1126

    Article  Google Scholar 

  10. Kumar A, Bayoumi M (1999) Multiple voltage-based scheduling methodology for low power in the high level synthesis. In: Proceedings of the international symposium on circuits and systems (ISCAS), pp 371–379

  11. Murugavel AK, Ranganathan N (2003) A game theoretic approach for power optimization during behavioral synthesis. IEEE Trans Very Large Scale Integr (VLSI) Syst 11(6):1031–1043

    Article  Google Scholar 

  12. Brayton RK, Camposano R, De Micheli G, Otten R, van Eijndhoven J (1988) The Yorktown silicon compiler system. In: Gajski DD (ed) Silicon Compilation. Addison-Wesley, Reading, pp 204–310

    Google Scholar 

  13. Nepomnyashchiy OV, Ryjenko IV, Shaydurov VV, Sirotinina NY, Postnikov AI (2018) The VLSI high-level synthesis for building onboard spacecraft control systems. In Anisimov K et al (eds). Proceedings of the scientific-practical conference research and development 2016. Springer, Cham, pp 229–238

  14. Mohanty SP, Velagapudi R, Kougianos E (2006) Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits. In: Proceedings of the conference on design, automation and test in Europe, pp 1191–1196, 6–10 March 2006

  15. Devadas S, Newton AR (1989) Algorithms for hardware allocation in data path synthesis. IEEE Trans Comput Aided Des Integr Circuits Syst 8(7):768–781

    Article  Google Scholar 

  16. Nestor JA, Krishnamoorthy G (1993) SALSA: a new approach to scheduling with timing constraints. IEEE Trans Comput Aided Des Integr Circuits Syst 12:1107–1122

    Article  Google Scholar 

  17. Lucia S, Navarro D, Lucia O, Zometa P, Findeisen R (2018) Optimized FPGA implementation of model predictive control for embedded systems using high-level synthesis tool. IEEE Tran Ind Inform 14(1):137–145

    Article  Google Scholar 

  18. De Micheli G (1994) Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York

    Google Scholar 

  19. Camposano R (1991) Path-based scheduling for synthesis. IEEE Trans Comput Aided Des 10:85–93

    Article  Google Scholar 

  20. Gerez SH (2004) Algorithms for VLSI design automation. Wiley, New York

    Google Scholar 

  21. Parker AC, Pizarro JT, Mlinar M (1986) Maha: a program for datapath synthesis. In: Proceedings of the 23rd ACM/IEEE design automation conference, 29 June–2 July 1986, pp 461–466

  22. Bhadauria S, Sengupta A (2015) Adaptive bacterial foraging driven datapath optimization: exploring power-performance tradeoff in high level synthesis. Appl Math Comput 269:265–278

    MathSciNet  MATH  Google Scholar 

  23. Krishnan V, Katkoori S (2006) A genetic algorithm for the design space exploration of datapaths during high-level synthesis. IEEE Trans Evol Comput 10(3):213–229

    Article  Google Scholar 

  24. Sengupta A, Sedaghat R (2011) Integrated scheduling, allocation and binding in high level synthesis using multi structure Genetic Algorithm based design space exploration. In: Proceedings of the 12th international symposium on quality electronic design, pp 1–9, 14–16 March 2011

  25. Harish Ram DS, Bhuvaneswari MC, Prabhu SS (2012) A novel framework for applying multiobjective GA and PSO based approaches for simultaneous area, delay, and power optimization in high level synthesis of datapaths. VLSI Des 2012:2–2. https://doi.org/10.1155/2012/273276

    Article  MathSciNet  Google Scholar 

  26. Abdel-kader RF (2008) Particle swarm optimization for constrained instruction scheduling. VLSI Des 2008(4):1–7. https://doi.org/10.1155/2008/930610

    Article  Google Scholar 

  27. Hashemi SA, Nowrouzian B (2012) A novel particle swarm optimization for high-level synthesis of digital filters. In: Proceedings of the 25th IEEE international symposium on circuits and systems. pp 580–583, 20–23 May 2012

  28. Pilato C, Loiacono D, Tumeo A, Ferrandi F, Lanzi PL, Sciuto D (2010) Speeding-up expensive evaluations in high-level synthesis using solution modeling and fitness inheritance. Comput Intell Expens Optim Probl 2:701–723

    Google Scholar 

  29. Wang G, Gong W, DeRenzi B, Kastner R (2006) Design space exploration using time and resource duality with the ant colony optimization. In: Proceedings of the 43rd ACM/IEEE design automation conference, pp 451–454, 24–28 July 2006

  30. Gopalakrishnan C, Katkoori S (2004) Tabu search based behavioral synthesis of low leakage datapaths. In: IEEE computer society annual symposium on VLSI, pp 260–261, 19–20 Feb. 2004

  31. Mohanty SP, Ranganathan N, Kougianos E, Patra P (2008) Low-power high-level synthesis for nanoscale CMOS circuits. Springer, Berlin

    Google Scholar 

  32. Mirjalili S (2015) Moth-flame optimization algorithm: a novel nature-inspired heuristic paradigm. Knowl Based Syst 89:228–249

    Article  Google Scholar 

  33. Bhuvaneswari MC (2015) Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems. Springer, Berlin

    Book  MATH  Google Scholar 

  34. Garima MJ, Loohani H (2016) Design, implementation and performance comparison of multiplier topologies in power-delay space. Eng Sci Technol Int J 19(1):355–363

    Google Scholar 

  35. Choong SS, Wong LP, Lim CP (2019) An artificial bee colony algorithm with a modified choice function for the traveling salesman problem. Swarm Evol Comput 44:622–635

    Article  Google Scholar 

  36. Karaboga D, Gorkemli B (2019) Solving traveling salesman problem by using combinatorial artificial bee colony algorithms. Int J Artif Intell Tools 28(1):1950004. https://doi.org/10.1142/S0218213019500040

    Article  Google Scholar 

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Correspondence to Seyed Hamid Zahiri.

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Esmaeili, M.R., Zahiri, S.H. & Razavi, S.M. A novel method for high-level synthesis of datapaths in digital filters using a moth-flame optimization algorithm. Evol. Intel. 13, 399–414 (2020). https://doi.org/10.1007/s12065-019-00302-w

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