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A formal study of two physical countermeasures against side channel attacks

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Abstract

Secure electronic circuits must implement countermeasures against a wide range of attacks. Often, the protection against side channel attacks requires to be tightly integrated within the functionality to be protected. It is now part of the designer’s job to implement them. But this task is known to be error-prone, and with current development processes, countermeasures are evaluated often very late (at circuit fabrication). To improve the confidence of the designer in the efficiency of the countermeasure, we suggest in this article to resort to formal methods early in the design flow for two reasons. First of all, we intend to check that the process of transformation of the design from the vulnerable description to the protected one does not alter the functionality. Second, we wish to prove that the security properties (that can derive from a formal security functional specification) are indeed met after transformation. Our first contribution is to show how such a framework can be setup (in COQ) for netlist-level protections. The second contribution is to illustrate that this framework indeed allows to detect vulnerabilities in dual-rail logics, with the examples of wave differential dynamic logic and balanced cell-based differential logic.

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Acknowledgments

The authors wish to thank Renaud Pacalet, from LabSoC (Sophia-Antipolis, France), for insightful comments and pieces of advice. We are also grateful to the anonymous reviewers of PROOFS 2012 (Leuven, Belgium), who helped improve the preliminary version of this paper. This work has been supported partly by the French research agency (ANR), via the “SEFPGA” project (Secure embedded Field Programmable Gates Array), also endorsed by the System@tic competitivity cluster, and the joint French-Japan ANR-JSP “SPACES” project (Security evaluation of Physically Attacked Cryptoprocessors in Embedded Systems). Besides, this work has benefited from a grant funded by a French DoD (DGA) in the framework of the “BCDL” RAPID project.

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Authors and Affiliations

  1. Secure-IC S.A.S., 37/39 rue Dareau, 75014 , Paris, France

    Sébastien Briais

  2. Institut Mines-Télécom, Télécom Paristech, 46 rue Barrault, 75634 , Paris Cedex 13, France

    Jean-Luc Danger & Sylvain Guilley

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  1. Sébastien Briais
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  2. Jean-Luc Danger
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  3. Sylvain Guilley
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Corresponding author

Correspondence to Sylvain Guilley.

Appendix A: Formalisation in the COQ proof assistant

Appendix A: Formalisation in the COQ proof assistant

In this appendix section, we give a flavour of the COQ formalisation.

1.1 Combinational circuits

We define the type of gates as a record type parametrised by the type A of the alphabet on which the gates operate. The words over A are simply represented by list of elements of type A.

We assume that the gates come with a typing function gate_wf and a partial evaluation function gate_eval. The two properties gate_eval_wf_prop and gate_wf_eval _prop express the fact that the typing function and the evaluation function are defined consistently, as we explained in Sect. 3.3.

figure a2

The type of combinational circuits is an inductive type parametrised by the type of underlying gates.

figure a3

The circuits \((\mathbf{I }^n)_{n \in \mathbb{N }}\) are computed by a recursive function in COQ.

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Briais, S., Danger, JL. & Guilley, S. A formal study of two physical countermeasures against side channel attacks. J Cryptogr Eng 3, 169–180 (2013). https://doi.org/10.1007/s13389-013-0054-6

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