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Mapping of Trellises Associated with General Encoders onto High-Performance VLSI Architectures

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Abstract

A rate 1/n binary generic convolutional encoder is a shift-register circuit where the inputs EquationSource % MathType!MTEF!2!1!+-% feaafiart1ev1aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLn% hiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr% 4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq-Jc9% vqaqpepm0xbba9pwe9Q8fs0-yqaqpepae9pg0FirpepeKkFr0xfr-x% fr-xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaGaamyEamaaBa% aaleaacaWGRbaabeaaaaa!3807!<![CDATA[$$\left( {\Delta \theta ,\Delta f} \right)$$ are information bits and the outputs EquationSource % MathType!MTEF!2!1!+-% feaafiart1ev1aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLn% hiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr% 4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq-Jc9% vqaqpepm0xbba9pwe9Q8fs0-yqaqpepae9pg0FirpepeKkFr0xfr-x% fr-xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaGaamyEamaaBa% aaleaacaWGRbaabeaaaaa!3807!<![CDATA[$$\left( {\Delta \theta ,\Delta f} \right)$$ are blocks of n bits generated as linear combinations on the appropriate shift register contents. The decoding of the outputs of a convolutional encoder can be carried out by the well-known Viterbi algorithm. The communication pattern of the Viterbi Algorithm is given as a graph, called trellis, associated to the state diagram of the corresponding encoder. In this paper we present a methodology that permits the efficient mapping of the Viterbi algorithm onto a column of an arbitrary number of processors. This is done through the representation of the data flow by using mathematical operators which present an inmediate hardware projection. A single operator string has been obtained to represent a generic encoder through the study of the data flow of free-forward encoders and feed-back encoders. The formal model developed is employed for the partitioning of the computations among an arbitrary number of processors in such a way that the data are recirculated opimizing the use of the processors and the communications. As a result, we obtain a highly regular and modular architecture suitable for VLSI implementation.

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References

  1. G.D. Forney, “The Viterbi Algorithm”, Proc. ofthe IEEE, vol. 61, no. 3, March 1973, pp. 268–278.

    Article  MathSciNet  Google Scholar 

  2. G. Ungerboeck, “Channel Coding with Multilevel/phase signals”, IEEE Trans. Inform. Theory, vol. 28, January 1982, pp. 55–67.

    Article  MATH  Google Scholar 

  3. M.W. Marcellin, T.R. Fischer. “Trellis Coded Quantization of Memoryless and Gauss-Markov sources”, IEEE Trans. Commun., vol. 28, January 1990, pp. 92–93.

    MathSciNet  Google Scholar 

  4. M.W. Marcellin, P. Sriram. K-L Tong, “Transform Coding of Monochrome and Color Images Using Trellis Coded Quantization”, IEEE Trans. on Circuits and Syst. for Video Tech. vol. 3, no. 4. August 1993, pp. 270–276.

    Article  Google Scholar 

  5. S.C. Glinski, T.M. Lalumia, D.R. Cassiday, T. Koh, C.M. Gerveshi, A. Wilson and J. Kumar, “A processor for graph search algorithms”, Proc. ISSCC'87, New York, 1987, pp. 162–163.

  6. C-Y Chang, K. Yao, “Systolic array processing of the Viterbi Algorithm”, IEEE. Trans. on inf. Theory, vol. 35, no. l, January 1989, pp. 76–86.

    Article  MathSciNet  MATH  Google Scholar 

  7. C.Y. Chang, K. Yao, “Viterbi decoding by a systolic array”, Proc. Twenty-Third Annu. Alleron Conf Commmun., Contr., Computing, Monticello, IL, Cot. 1985, 1985, pp. 430–439.

    Google Scholar 

  8. P.G. Gulak, T. Kailath, “Locally connected VLSI architectures for the Viterbi Algorithm”, IEEE J. Sleet. Areas Commun., vol. 6, April 1988, pp. 527–538.

    Article  Google Scholar 

  9. F. Daneshgaran, K. Yao, “The Iterative Collapse Algorithm: A Novel Approach for the Design of Long Constraint Length Viterbi Decoders-Part I”, IEEE Trans. on Communications, vol. 43, no. 2/3/4, 1995, pp. 1409–1418.

    Article  MATH  Google Scholar 

  10. H Li, C. Chakrabarti, “A New Architecture for the Viterbi Decoder for Code Rate kin”, IFFF Trans, on Communications, vol. 44, no. 2, 1996, pp. 158–164.

    Article  MATH  Google Scholar 

  11. S. Bitterlich, H. Meyr, “Efficient Scalable Architecture for Viterbi Decoders”, Proc. of the Int. Conf on Application Specific Array Processors. ASAP'93, 1993, pp. 89–100.

  12. C.B. Shang, H-D. Ling, R. Cypher, P.H. Siegel, H.K. Thapar, ”Area-Efficient Architectures for the Viterbi Algorithm-Partl: Theory”, IEEE Trans. On. Communications, vol. 41, no. 4, April 1993, pp. 636–644

    Article  Google Scholar 

  13. C.B. Shung, H-D. Ling, R. Cypher, P.H. Siegel. H.K. Thapar, ”Area-Efficient Architectures for the Viterbi Algorithm-PartII: Applications”, IEEE Trans. On. Communications, vol. 41, no. 5, May 1993, pp. 802–807.

    Article  MATH  Google Scholar 

  14. F. Arguello. J.D. Bruguera, R. Doallo and E.L. Zapata, “Parallel Architecture for Fast Transforms with Trigonometric Kernel”, IEEE Trans. on Parallel and Distributed Systems, vol. 5, no. 10, 1994, pp. 1091–1099.

    Article  Google Scholar 

  15. E.L. Zapata and F. Argilello. “Aplication-Specific Architecture for Fast Transforms based on the Succesive Doubling Method”, IEEE Trans. on Signal Processing, vol. 41, no. 3, 1993, pp. 1476–1481.

    Article  Google Scholar 

  16. J. López and E.L. Zapata, “Unified Architecture for Divide and Conquer based Tridiagonal System Solvers”, IEEE Trans. on Computers, vol. 43, 1994, pp. 1413–1425.

    Article  Google Scholar 

  17. M. Bóo, F. Arguello, J.D. Bruguera, R. Doallo, E.L. Zapata, “High-Performance VLSI Architecture for the Viterbi Algorithm”, IEEE Trans. on Communications, vol. 45, no. 2, February 1997, pp. 168–176.

    Article  Google Scholar 

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Authors and Affiliations

  1. Department of Electronics, University of Santiago de Compostela, Spain

    Montserrat Bóo, Francisco Argüello & Javier D. Bruguera

  2. Department of Computer Architecture, University of Málaga, Spain

    Emilio L. Zapata

Authors
  1. Montserrat Bóo
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  2. Francisco Argüello
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  3. Javier D. Bruguera
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  4. Emilio L. Zapata
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Bóo, M., Argüello, F., Bruguera, J.D. et al. Mapping of Trellises Associated with General Encoders onto High-Performance VLSI Architectures. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 17, 57–73 (1997). https://doi.org/10.1023/A:1007949000569

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