Abstract
A rate 1/n binary generic convolutional encoder is a shift-register circuit where the inputs EquationSource % MathType!MTEF!2!1!+-% feaafiart1ev1aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLn% hiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr% 4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq-Jc9% vqaqpepm0xbba9pwe9Q8fs0-yqaqpepae9pg0FirpepeKkFr0xfr-x% fr-xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaGaamyEamaaBa% aaleaacaWGRbaabeaaaaa!3807!<![CDATA[$$\left( {\Delta \theta ,\Delta f} \right)$$ are information bits and the outputs EquationSource % MathType!MTEF!2!1!+-% feaafiart1ev1aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLn% hiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr% 4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq-Jc9% vqaqpepm0xbba9pwe9Q8fs0-yqaqpepae9pg0FirpepeKkFr0xfr-x% fr-xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaGaamyEamaaBa% aaleaacaWGRbaabeaaaaa!3807!<![CDATA[$$\left( {\Delta \theta ,\Delta f} \right)$$ are blocks of n bits generated as linear combinations on the appropriate shift register contents. The decoding of the outputs of a convolutional encoder can be carried out by the well-known Viterbi algorithm. The communication pattern of the Viterbi Algorithm is given as a graph, called trellis, associated to the state diagram of the corresponding encoder. In this paper we present a methodology that permits the efficient mapping of the Viterbi algorithm onto a column of an arbitrary number of processors. This is done through the representation of the data flow by using mathematical operators which present an inmediate hardware projection. A single operator string has been obtained to represent a generic encoder through the study of the data flow of free-forward encoders and feed-back encoders. The formal model developed is employed for the partitioning of the computations among an arbitrary number of processors in such a way that the data are recirculated opimizing the use of the processors and the communications. As a result, we obtain a highly regular and modular architecture suitable for VLSI implementation.
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Bóo, M., Argüello, F., Bruguera, J.D. et al. Mapping of Trellises Associated with General Encoders onto High-Performance VLSI Architectures. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 17, 57–73 (1997). https://doi.org/10.1023/A:1007949000569
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DOI: https://doi.org/10.1023/A:1007949000569