Abstract
This paper describes how the real-time bandwidth of a radial basis neural network (RBNN) can be improved by the use of a field programmable gate array (FPGA). Accelerated performance is gained by moving the time-consuming RBNN exponential calculations from a general purpose processor to a dedicated FPGA that implements an optimized CORDIC-algorithm. The design methodology is presented and illustrated with a speech recognition application.
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Meyer-Bäse, U., Meyer-Bäse, A., Mellott, J. et al. A Fast Modified CORDIC—Implementation of Radial Basis Neural Networks. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 20, 211–218 (1998). https://doi.org/10.1023/A:1008006030955
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DOI: https://doi.org/10.1023/A:1008006030955