Abstract
In this paper we present our studies for implementing complex DSP and Telecom systems in FPGAs. We analyse suitability of FPGA device architectures for implementing complex algorithms. Here we use a Viterbi algorithm as a deeper case study. Different architectural strategies for implementations are discussed and analysed with the special emphasis on practical FPGA implementations. Speed performance, easy routability and minimisation of inter-chip communication are used as design criteria. Viterbi decoder, constraint length seven, was designed and simulated with VHDL in Synopsys and Mentor tool environments and further implemented on four Xilinx 4028EX devices using trace-back based architecture. Also partitioning aspects of the decoding algorithm are presented and analysed.
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Kivioja, M., Isoaho, J. & Vänskä, L. Design and Implementation of Viterbi Decoder with FPGAs. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 21, 5–14 (1999). https://doi.org/10.1023/A:1008067404215
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DOI: https://doi.org/10.1023/A:1008067404215