Abstract
Determining a tight WCET of a block of code to be executed on a modern superscalar processor architecture is becoming ever more difficult due to the dynamic behaviour exhibited by current processors, which include dynamic scheduling features such as speculative and out-of-order execution in the context of multiple execution units with deep pipelines. We describe the use of Coloured Petri Nets (CP-nets) in a simulation based approach to this problem. A complex model of a generic processor architecture is described, with emphasis on the modelling strategy for obtaining the WCET and an analysis of the results.
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Appel, A. W., and MacQueen, D. B. 1991. Standard ML of New Jersey. In Third Int. Symp. on Programming Languages Implementation and Logic Programming, Maluszyński, J., and Wirsing, M., eds. Lecture Notes on Computer Science, Volume 528, Springer.
Arvind, D. K., and Rebello, V. E. F. 1994. Instruction-level parallelism in asynchronous processor architectures. In Proceedings of the Third Int. Workshop on Algorithms and Parallel VLSI Architectures, Moonen, M., and Catthoor, F., eds. Elsevier Science Publishers, Leuven, Belgium, pp. 203–215.
Burns, F. P., Koelmans, A. M., and Yakovlev, A. V. 1999. Analysing superscalar processor architectures with coloured Petri nets. Int. J. Software Tools for Technology Transfer 2: 182–191.
Choi, J., Lee, J., and Kong, I. 1994. Timing Analysis of Superscalar Programs using ACSR. Technical report, Dept. of Computer and Information Science, University of Pennsylvania.
Christensen, S., Jorgensen, J. B., and Kristensen, L.M. 1997. Design/CPN-A computer tool for coloured Petri nets. In Proceedings of Tacas '97, Brinksma, E., ed. Lecture Notes on Computer Science, Volume 1217, Springer, pp. 209–223.
Diep, T. A. 1995. A visualization based microarchitecture workbench. Proc. Caregie Mellon University, PhD Thesis.
Healy, C., Whalley, D. B., and Harmon, M. G. 1995. Integrating the timing analysis of pipelining and instruction caching. Proc. 16th Conf. Real-Time Systems Symposium.
Jensen, K. 1997. Coloured Petri nets. Basic concepts, analysis methods and practical use. Volume 1, Basic concepts. EATCS Monographs in Theoretical Computer Science, Springer-Verlag, ISBN 3-540-58276-2.
Johnson, M. 1991. Superscalar Microprocessor Design. Prentice Hall.
Li, Y. S., Malik, S., and Wolfe, A. 1995. Performance estimation of embedded software with instruction cache modelling. Proc. Int. Conf. Computer Aided Design.
Lim, S. S., Bae, Y. H., Jang, G. T., Rhee, B. D., Min, S. L., Park, C. Y., Shin, H., Park, K., and Kim, C. S. 1994. An accurate worst case timing analysis technique for RISC processors. Proc 15th IEEE Real-Time Systems Symp.: 97–108.
Lim, S. S., Han, J. H., Kim, J., and Min, S. L. 1998. A worst case timing analysis technique for multiple-issue machines. Proc. 19th Conf. Real-Time Systems Symposium.
Narasimham, K., and Nilsen, K. D. 1994. Portable execution time analysis for RISC processors. Languages, Compilers, and Tools for Real-Time Systems.
Park, C. Y. 1993. Predicting program execution times by analyzing static and dynamic program paths. J. Real Time Systems 5(1): 31–61.
Puschner, P., and Koza, C. 1989. Calculating the maximum execution time of real-time programs. J. Real Time Systems 1(2): 159–176.
Razouk, R. R. 1987. The use of Petri nets for modeling pipelined processors. Technical Report 87-29, University of California, Department of Information and Computer Science.
Shaw, A. C. 1989. Reasoning about time in higher-level language software. IEEE Trans. Software Engineering 15(7): 875–889.
Schneider, J., and Ferdinand, C. 1999. Pipeline behaviour prediction for superscalar processors by abstract interpretation. Languages, Compilers, and Tools for Embedded Systems.
Zhang, N. N., Burns, A., and Nicholson, M. 1993. Pipelined processors and worst case execution times. J. Real Time Systems 5(4).
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Burns, F., Koelmans, A. & Yakovlev, A. WCET Analysis of Superscalar Processors Using Simulation With Coloured Petri Nets. Real-Time Systems 18, 275–288 (2000). https://doi.org/10.1023/A:1008101416758
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DOI: https://doi.org/10.1023/A:1008101416758