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A Hierarchical Block-Floating-Point Arithmetic

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Abstract

In order to give an answer to a question of the arithmetic in future DSP architectures for mobile communication applications, the signal processing quality of different arithmetic representations has been studied. Based on the result, a new approach for implementing block-floating-point arithmetic is proposed. This approach intends to preserve the least-significant-bits (LSBs) to improve signal processing quality. The preservation of LSBs is automatically and perfectly done by hardware. Serveral simulation results show that the proposed block-floating-point implementation provides improved SNRs over conventional block-floating-point implementations. For the same number of bits in the memory for each representation, the SNRs better than floating-point are also observed. For multiple datapath DSPs, this implementation also requires significantly less hardware complexity than floating-point.

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Authors and Affiliations

  1. Mobile Communications Systems, Dresden University of Technology, 01026, Dresden, Germany

    Shiro Kobayashi & Gerhard P. Fettweis

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  1. Shiro Kobayashi
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  2. Gerhard P. Fettweis
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Kobayashi, S., Fettweis, G.P. A Hierarchical Block-Floating-Point Arithmetic. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 24, 19–30 (2000). https://doi.org/10.1023/A:1008110410087

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  • DOI: https://doi.org/10.1023/A:1008110410087

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