Abstract
High-level specifications for the behaviour of information processing systems consist of data and control flow descriptions as well as of timing requirements, which are to be met by feasible implementations. In contrast to systems specified as task graphs this approach is based on a functional partitioning. A process net description with conditional process activation is proposed. Furthermore, the simulation of token flow leads to a schedule that supports investigations of the timing analysis for the proposed Codesign Model (CDM). Predictions of the delay between any two processes of the system are also possible, as well as the processing speed of primary inputs and outputs, iteration times of determined periods, and hence, all derivable time criteria. A formal notation of process nets as cyclic graphs is given, which is shown to be useful for the description of complex digital embedded systems. The properties of the processes involved are detailed. In general, scheduling with resource allocation on a graph structure, as discussed in this paper, is NP-complete. However, the advocated simulation method delivers detailed information on conditional paths of data and control flow in a CDM. The simulation can be interrupted at any point in time for an evaluation of corresponding results and for a subsequent refinement of the CDM. The outlined approach is intended for a capture and an accessment of specifications in the conceptual phase of system development. Resulting advantages and some restrictions are demonstrated by means of an image processing system.
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Boßung, W., Huss, S.A. & Klaus, S. High-Level Embedded System Specifications Based on Process Activation Conditions. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 21, 277–291 (1999). https://doi.org/10.1023/A:1008191425265
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DOI: https://doi.org/10.1023/A:1008191425265