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An Efficient Critical Path Tracing Algorithm for Designing High Performance Vlsi Systems

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Abstract

Fast and correct timing verification is a critical issue in VLSIdesign. Several timing verification algorithms have been proposed in thelast few years. However, due to the huge computation time needed toeliminate false paths, existing algorithms have difficulty in performingtiming verification for large circuits. This paper presents efficientcritical path analysis algorithm based on test pattern generation with a newsensitization criterion. The algorithm does not require generation of a pathlist and elimination of false paths to find out the correct critical path ofthe circuit. The inputs which sensitize the critical path are determined aswell. The efficiency and speed of our algorithm are demonstrated using theISCAS benchmark circuits, and the critical paths are found in vastlyimproved times.

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Authors and Affiliations

  1. School of Computing, Soongsil University, Seoul, Korea, 156-743

    Hoon Chang & Jacob a. Abraham

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  1. Hoon Chang
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  2. Jacob a. Abraham
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Chang, H., Abraham, J.a. An Efficient Critical Path Tracing Algorithm for Designing High Performance Vlsi Systems. Journal of Electronic Testing 11, 119–129 (1997). https://doi.org/10.1023/A:1008214321624

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