Abstract
An important problem one faces during design of a built-in self-test(BIST) based delay test is the selection of a proper generator toapply the test vectors. This problem is due to the need of applyinga pair of patterns to detect any given delay fault. The secondvector has to be launched against the logic immediately following thefirst vector. This timing requirement places severe restrictions onthe kind of hardware suitable for the task, especially in built-inself-test applications where the generator must reside on chip.
This paper studies the various options one has in designing the delay test vector generator. Both scan and non-scan designs are addressed. Thedifferent options are measured based on their performance, cost, and flexibility.
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Savir, J. Delay Test Generation: A Hardware Perspective. Journal of Electronic Testing 10, 245–254 (1997). https://doi.org/10.1023/A:1008219725676
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DOI: https://doi.org/10.1023/A:1008219725676