Skip to main content
Log in

The Design and Implementation of an On-Line Testable UART

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

This paper presents the design of a complex integrated circuit realised through a novel on-line test methodology. The circuit and its exact conventional equivalent both have been realised in FPGA technology. As such it represents one of the most complex designs realised to date using on-line test approaches. The approach used—IFIS incorporates dual-rail coding of individual data and a handshaking protocol, which substantially simplifies the detection of failure. Details of the IFIS methodology are given. The IFIS and conventional redesign of a commercial UART are reported, focusing on methodological issues as well as size and speed. Output traces are shown for the IFIS UART on FPGA operating under fault-free conditions and with deliberate failures injected.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. M. Saeed, D. Thulborn, J. Yeandel, and S. Jones, “IFIS—AnOn-Line Testing Methodology Using Dual-Rail Data Coding,” Proc. 2nd IEEE International On-Line Testing Workshop, Biarritz, July 1996, pp. 68–71.

  2. S.R. Jones and D.W. Lloyd, “Digital Circuits,” UK Patent Application. 9225327.8, Dec. 1991.

  3. H. Hulgaard, S.M. Burns, and G. Borriello, “Testing Asynchronous Circuits: A Survey,” Technical Report 94–03–06, Department of Computer Science and Engineering, FR-35, University of Washington, March 1994.

  4. V.N. Yarmolik, Fault Diagnosis of Digital Circuits, John Wiley & Sons, 1990.

  5. I. David, R. Ginosar, and M. Yoeli, “Implementing Sequential Machines as Self-Timed Circuits,” IEEE Trans. Comput., Vol. 41, No. 1, pp. 12–17, Jan. 1992.

    Google Scholar 

  6. D.W. Lloyd and S.R. Jones, “Improved Self-Timed Circuit Design,” Electronic Letters, Vol. 28, No. 5, pp. 492–494.

  7. M. Dean, T. Williams, and D. Dill, “Efficient Self-timing with Level-Encoded 2-Phase Dual-Rail (LEDR),” MIT Conference on Advanced Research in VLSI, March 1991, pp. 55–70.

  8. C. Mead and L. Conway, “Introduction to VLSI Systems,” Addison-Wesley, Reading, MA, 1980, pp. 218–262.

    Google Scholar 

  9. V. Varshavsky, Self-Timed Control of Concurrent Processes, Kluwer Academic Publishers, 1986, pp. 309–328.

  10. R.C. Aitken, “Diagnosis of Leakage Faults with Iddq,” Journal of Electronic Testing: Thoery and Applications, Vol. 3, pp. 367–375, 1992.

    Google Scholar 

  11. S. Chakravarty and S. Suresh, “Iddq Measurement Based Diagnosis of Bridging Faults in Full Scan Circuits,” 7th International Conference on VLSI Design, Jan. 1994, pp. 179–182.

  12. V. Champac, R. Rodrigez-Montanes, J.A. Segura, J. Figueras, and J.A. Rubio, “Fault Modelling of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS Circuits,” European Test Conference, April 1991, pp. 143–156.

  13. J. Ferguson and T. Larrabee, “Test Pattern Generation for Realistic Bridge Faults in CMOS IC's,” Proc. International Test Conference, 1991, pp. 492–499.

  14. D. Pradhan, and J. Stiffler, “Error Correcting Codes and Self-Checking Circuits,” IEEE Computer, pp. 27–35, March 1980.

  15. S.J. Piestrak, “Design of Self-Testing Checkers for Unidirectional Error Detecting Codes,” ISSN 0324–9786, Oficyna Wydawnicza Politechniki Wroclawskeij, Wroclaw, 1995.

    Google Scholar 

  16. J. Shedletsky, “Error Correction by Alternate-Data Retry,” IEEE Trans. Comput., Vol. C-27, No. 2, pp. 106–112, Feb. 1978.

    Google Scholar 

  17. J. Yeandel, D. Thulborn, M. Saeed, and S. Jones, “Fault Localisation for On-Line Testable Designs Realised Using Dual-Rail Design Methodology,” Proc. 2nd IEEE International On-Line Testing Workshop, Biarritz, July 1996, pp. 221–222.

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

About this article

Cite this article

Yeandel, J., Thulborn, D. & Jones, S. The Design and Implementation of an On-Line Testable UART. Journal of Electronic Testing 12, 187–198 (1998). https://doi.org/10.1023/A:1008220515881

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1008220515881

Navigation