Abstract
Advances in reducing size and increasing functionality of electronics have been due primarily to the shrinking geometries and increasing performance of integrated circuit technologies. Recently, development efforts aimed at reducing size and increasingfunctionality have focused on the first level of the electronicpackage. The result has been the development of multichip packaging,technologies in which bare IC chips are mounted on a single high density substrate that serves to “package” thechips, as well as interconnect them. A number of benefits accruebecause of multichip packaging, namely, increased chip density,space savings, higher performance, and less weight. Therefore, thesetechnologies are attractive for today's light weight, portable, highperformance electronic equipment and devices.
In spite of these benefits, multichip packaging has not shown the kind of explosive growth and expansion that was predicted[1]. A major inhibitor for these technologies has been theavailability of fully tested and conditioned bare die, or“known good die”. This paper reviews the issues and technologies associated with test and burn-in of bareor minimally packaged IC products.
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Gilg, L. Known Good Die. Journal of Electronic Testing 10, 15–25 (1997). https://doi.org/10.1023/A:1008262229133
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DOI: https://doi.org/10.1023/A:1008262229133