Abstract
Path delay fault model is the most suitable model for detectingdistributed manufacturing defects which can cause delayfaults. However, the number of paths in a modern design can beextremely large and the path delay testability of many practicaldesigns is very low. In this paper we show how to resynthesize acombinational circuit in order to reduce the total number of paths inthe circuit. Our results show that it is possible to obtain circuitswith a significant reduction in the number of paths while notincreasing area and/or delay of the longest sensitizable path in thecircuit.
Research on path delay testing shows that in many circuits a largeportion of paths does not have a test that can guarantee detection ofa delay fault. The path delay testability of a circuit would increaseif the number of such paths is reduced. We show that addition of asmall number of test points into the circuit can help reducing thenumber of such paths in the given design.
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Krstić, A., Cheng, KT. Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability. Journal of Electronic Testing 11, 43–54 (1997). https://doi.org/10.1023/A:1008295716980
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DOI: https://doi.org/10.1023/A:1008295716980