Abstract
A novel built-in self-test (BIST) architecture and a test pattern generator (TPG) design methodology to program this architecture are presented for inter-IC interconnects among combinational non-boundary scan ICs (often called cluster-ICs) via IEEE 1149.1 boundary scan architecture (BSA). Due to the expense and complexity of BSA circuitry, cluster-ICs are still widely used in modern circuit boards. Since combinational logic and 3-state cluster nets exist within cluster interconnect, in order to test all detectable faults in inter-IC nets that include cluster-ICs, newly identified TPG requirements are used to guarantee fault coverage during the design of proposed BIST architecture. This architecture contains a two-level C-TPG that generates constrained pseudo-random patterns for boundary scan cells (BSCs) of cluster control cones, a D-TPG that generates patterns for BSCs of cluster data cones, and a look-up table which is programmed to select, for each BSC, a specific C-TPG or D-TPG stage whose content is shifted into that BSC. This test architecture provides a true BIST solution for cluster testing. The proposed methodology generates TPGs that (i) guarantee the avoidance of multi-driver conflicts when testing via BSA, (ii) guarantee the detection of all testable interconnect faults, (iii) have low area overheads, and (iv) have short test lengths.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
IEEE, IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE, 1993.
C.-H. Chiang and S.K. Gupta, “BIST TPGs for Faults in Board Level Interconnect via Boundary Scan,” Proceedings IEEE VLSI Test Symposium, 1997, pp. 376-382.
W. Daniel, “Optimizing Fault Detection for Boundary-Scan Testing,” Integrated System Design Magazine, Sept. 1995.
P. Hansen, “Testing Conventional Logic and Memory Clusters Using Boundary Scan Devices as Virtual ATE Channels,” Proceedings IEEE International Test Conference, 1989, pp. 166-173.
M.F. Lefebvre, “Test Generation: A Boundary Scan Implementation for Module Interconnect Testing,” Proceedings IEEE International Test Conference, 1991, pp. 88-95.
C.-H. Chiang, “Built-In Self-Test for Iinterconnect Faults via Boundary Scan,” PhD Thesis, Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, 1998.
A. Hassan, V.K. Agarwal, J. Rajski, and B. Nadeau-Dostie, “Testing of Glue Logic Interconnect using Boundary Scan Architecture,” Proceedings IEEE International Test Conference, 1989, pp. 700-711.
._ M. Melton and F. Brglez, “Automatic Pattern Generation for Diagnosis of Wiring Interconnect Faults.” Proceedings IEEE International Test Conference, 1992, pp. 389-398.
D. Sterba, A. Halliday, and D. McClean, “ATPG Issues for Board Designs Implementing Boundary Scan,” Proceedings IEEE International Test Conference, 1990, pp. 243-251.
A. Flint, “A Simulation-Based JTAG ATPG Optimized for MCMs,” Proceedings IEEE International Test Conference, 1997, pp. 101-105.
C. Su, S.-S. Hwang, S.-J. Jou, and Y.-T. Ting, “Syndrome Simulation and Syndrome Test for Unscanned Interconnects,” Proceedings Asian Test Symposium, 1996, pp. 62-67.
M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, New York, N.Y., 1990.
Y.-S. Chang, Private communication, June 1998.
497AE and 1215E Boundary-Scan Master 2 User Manual, 1998. Lucent Technology Microelectronics.
N. Jarwala and C.W. Yau, “Achieving Board-Level BIST Using the Boundary-Scan Master,” Proceedings IEEE International Test Conference, 1991, pp. 649-658.
Rights and permissions
About this article
Cite this article
Chiang, CH., Gupta, S.K. BIST TPG for Combinational Cluster Interconnect Testing at Board Level. Journal of Electronic Testing 16, 427–442 (2000). https://doi.org/10.1023/A:1008308430051
Issue Date:
DOI: https://doi.org/10.1023/A:1008308430051