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Built-in Self Test Based on Multiple On-Chip Signature Checking

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Abstract

We propose an improved BIST architecture which supports on-chip comparison of signatures at no significant increase in area. The proposed test architecture reduces detection latency and eliminates the lengthy scan-out phase from each test session by allowing testing and on-chip signature comparison of multiple intermediate signatures to occur concurrently. The work is based on a novel procedure to implement the multiple on-chip signature checking. We show that such a test method gives significant improvements in test application time and aliasing probability. This paper also presented two techniques to minimize the test area overhead with a very small test time overhead compare to the conventional schemes. These techniques resulted in up to 80% savings in test area overhead for some High-level synthesis benchmark circuits. This paper also presents an aliasing analysis of the proposed scheme.

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Authors and Affiliations

  1. Department of Electrical and Electronic Engineering, Faculty of Engineering, University of Aden, Yemen

    Mohammed Fadle Abdulla

  2. Department of Electrical Engineering, Indian Institute of Technology, New Delhi, 110016, India

    C.P. Ravikumar

  3. Department of Computer Science & Engineering, Indian Institute of Technology, New Delhi, 110016, India

    Anshul Kumar

Authors
  1. Mohammed Fadle Abdulla
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  2. C.P. Ravikumar
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  3. Anshul Kumar
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Abdulla, M.F., Ravikumar, C. & Kumar, A. Built-in Self Test Based on Multiple On-Chip Signature Checking. Journal of Electronic Testing 14, 227–244 (1999). https://doi.org/10.1023/A:1008310203790

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  • DOI: https://doi.org/10.1023/A:1008310203790

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