Skip to main content
Log in

Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

We propose a new static test set compaction method based on a careful examination of attributes of fault coverage curves. Our method is based on two key ideas: (1) fault-list and test-set partitioning, and (2) vector re-ordering. Typically, the first few vectors of a test set detect a large number of faults. The remaining vectors usually constitute a large fraction of the test set, but these vectors are included to detect relatively few hard faults. We show that significant compaction can still be achieved by partitioning faults into hard and easy faults, and compaction is performed only for the hard faults. This significantly reduces the computational cost for static test set compaction without affecting quality of compaction. The second key idea re-orders vectors in a test set by moving sequences that detect hard faults to the beginning of the test set. Fault simulation of the newly concatenated re-ordered test set results in the omission of several vectors so that the compact test set is smaller than the original test set. Experiments on several ISCAS 89 sequential benchmark circuits and large production circuits show that our compaction procedure yields significant test set reductions in low execution times.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. S.K. Bommu, S.T. Chakradhar, and K.B. Doreswamy, “Vector Restoration Using Accelerated Validation and Refinement,” Proc. Asian Test Symp., 1998, pp. 458-466.

  2. A. Raghunathan and S.T. Chakradhar, “Acceleration Techniques for Dynamic Vector Compaction,” Proc. Intl. Conf. Computer-Aided Design, 1995, pp. 310-317.

  3. S.T. Chakradhar and A. Raghunathan, “Bottleneck Removal Algorithm for Dynamic Compaction and Test Cycles Reduction,” Proc. European Design Automation Conf., Sept. 1995, pp. 98-104.

  4. S.T. Chakradhar and A. Raghunathan, “Bottleneck Removal Algorithm for Dynamic Compaction in Sequential Circuits,” IEEE Trans. on Computer-Aided Design, Vol. 16, No. 10, pp. 1157-1172, Oct. 1997.

    Google Scholar 

  5. T.M. Niermann, R.K. Roy, J.H. Patel, and J.A. Abraham, “Test Compaction for Sequential Circuits,” IEEE Trans. Computer-Aided Design, Vol. 11, No. 2, pp. 260-267, Feb. 1992.

    Google Scholar 

  6. B. So, “Time-Efficient Automatic Test Pattern Generation System,” Ph.D. Thesis, EE Dept., Univ. of Wisconsin at Madison, 1994.

  7. I. Pomeranz and S.M. Reddy, “On Static Compaction of Test Sequences for Synchronous Sequential Circuits,” Proc. Design Automation Conf., June 1996, pp. 215-220.

  8. F. Corno, P. Prinetto, M. Rebaudengo, and M.S. Reorda, “New Static Compaction Techniques of Test Sequences for Sequential Circuits,” Proc. European Design&Test Conf., 1997, pp. 37-43.

  9. M.S. Hsiao, E.M. Rudnick, and J.H. Patel, “Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors,” Proc. IEEE VLSI Test Symp., April 1997, pp. 188-195.

  10. M.S. Hsiao and S.T. Chakradhar, “State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits,” Proc. Design, Automation, and Test in Europse (DATE) Conf., Feb. 1998, pp. 577-582.

  11. I. Pomeranz and S.M. Reddy, “Vector Restoration Based Static Compaction of Test Sequences for Synchronous Sequential Circuits,” Proc. International Conference on Computer Design, Oct. 1997, pp. 360-365.

  12. R. Guo, I. Pomeranz, and S.M. Reddy, “Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration,” Proc. Design, Automation, and Test in Europse (DATE) Conf., Feb. 1998, pp. 583-587.

  13. S.K. Bommu, S.T. Chakradhar, and K.B. Doreswamy, “Static Test Sequence Compaction Based on Segment Reordering and Fast Vector Restoration,” Proc. Intl. Test Conf., 1998, pp. 954-961.

  14. S.K. Bommu, S.T. Chakradhar, and K.B. Doreswamy, “Static Compaction Using Overlapped Restoration and Segment Pruning,” Proc. Intl. Conf. CAD, 1998, pp. 140-146.

  15. T.M. Niermann and J.H. Patel, “HITEC: A Test Generation Package for Sequential Circuits,” Proc. European Conf. Design Automation. EDAC/, 1991, pp. 214-218.

  16. M.S. Hsiao, E.M. Rudnick, and J.H. Patel, “Sequential Circuit Test Generation Using Dynamic State Traversal,” Proc. European Design and Test Conf., 1997, pp. 22-28.

  17. F. Brglez, D. Bryan, and K. Kozminski, “Combinational Profiles of Sequential Benchmark Circuits,” Int. Symposium on Circuits and Systems, 1989, pp. 1929-1934.

  18. M.S. Hsiao, E.M. Rudnick, and J.H. Patel, “Automatic Test Generation Using Genetically-Engineered Distinguishing Sequences,” Proc. VLSI Test Symp., 1996, pp. 216-223.

  19. E.M. Rudnick and J.H. Patel “Simulation-Based Techniques for Dynamic Test Sequence Compaction,” Proc. Intl. Conf. Computer-Aided Design, 1996, pp. 67-73.

  20. T.H. Cormen, C.E. Leiserson, and R.L. Rivest, Introduction to Algorithms, The MIT Press, Cambridge, MA, 1990.

    Google Scholar 

Download references

Authors

Rights and permissions

Reprints and permissions

About this article

Cite this article

Hsiao, M.S., Chakradhar, S. Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits. Journal of Electronic Testing 16, 329–338 (2000). https://doi.org/10.1023/A:1008313901938

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1008313901938

Navigation