Abstract
In this paper, we propose a controller resynthesis technique to enhance the testability of register-transfer level (RTL) controller/data path circuits. Our technique exploits the fact that the control signals in an RTL implementation are don't cares under certain states/conditions. We make an effective use of the don't care information in the controller specification to improve the overall testability (better fault coverage and shorter test generation time). If the don't care information in the controller specification leaves little scope for respecification, we add control vectors to the controller to enhance the testability. Experimental results with example benchmarks show an average increase in testability of 9% with a 3–4 fold decrease in test generation time for the modified implementation. The area, delay and power overheads incurred for testability are very low. The average area overhead is 0.4%, and the average power overhead is 4.6%. There was no delay overhead due to this technique in most of the cases.
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References
M. Abramovici, M. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, 1990.
K.T. Cheng and V.D. Agarwal, “A Partial Scan Method for Sequential Circuits with Feedback,” IEEE Trans. VLSI Systems, Vol. 39, pp. 544–548, April 1986.
V. Chickermane, E.M. Rudnick, P. Banerjee, and J.H. Patel, “Non-Scan Design-for-Testability Techniques for Sequential Circuits,” Proc. Int. Test Conf., June 1993, pp. 236–241.
S. Dey and M. Potkonjak, “Non-Scan Design-for-Testability Technique of RT-Level Circuits,” Proc. Int. Conf. Computer-Aided Design, Nov. 1994, pp. 640–645.
I. Ghosh, A. Raghunathan, and N.K. Jha, “Design for Hierarchical Testability of RTL Circuits Obtained by Behavioral Synthesis,” Proc. Int. Conf. Computer Design, Oct. 1995, pp. 173–179.
A. Ghosh, S. Devadas, and A.R. Newton, “Sequential Test Generation and Synthesis for Testability at the Register Transfer and Logic Levels,” IEEE Trans. Computer-Aided Design, Vol. 12, pp. 579–588, May 1993.
A. Majumdar, K. Saluja, and R. Jain, “Incorporating Testability Constraints in High-Level Synthesis,” Proc. Int. Symp. Fault-Tolerant Comput., July 1992, pp. 272–279.
S. Bhatia and N.K. Jha, “Genesis: A Behavioral Synthesis System for Hierarchical Testability,” Proc. European Design and Test Conf., Feb. 1993, pp. 272–276.
S. Dey, V. Gangaram, and M. Potkonjak, “A Controller-Based Design-for-Testability Technique for Controller-Datapath Circuits,” Proc. Int. Conf. Computer-Aided Design, Nov. 1995, pp. 534–540.
P. Vishakantaiah, T. Thomas, J.A. Abraham, and M.S. Abadir, “AMBIANT: Automatic Generation of Behavioral Modifications for Testability,” Proceedings of ICCD, Oct. 1993, pp. 63–66.
C.-H. Chen, T. Karnik, and D.G. Saab, “Structural and Behavioral Synthesis for Testability Techniques,” IEEE Trans. Computer-Aided Design, Vol. 13, pp. 777–785, June 1994.
F. Hsu, E.M. Rudnick, and J.H. Patel, “Enhancing High-Level Control-Flow for Improved Testability,” Proc. Int. Conf. Computer-Aided Design, Nov. 1996, pp. 322–328.
A. Raghunathan, S. Dey, N.K. Jha, and K. Wakabayashi, “Power Management Techniques for Control-Flow Intensive Designs,” Proc. Design Automation Conf., June 1997, pp. 429–434.
I. Ghosh, A. Raghunathan, and N.K. Jha, “A Design for Testability Technique of RTL Circuits using Control/Data Flow Extraction,” Proc. Int. Conf. Computer-Aided Design, Nov. 1996, pp. 329–336.
L. Avra, “Allocation and Assignment in High-Level Synthesis for Self-Testable Datapaths,” Proc. Int. Test Conf., June 1991, pp. 463–471.
E. Sentovich, K. Singh, C. Moon, H. Savoj, R. Brayton, and A. Sangiovanni-Vincentelli, “Sequential Circuit Design using Synthesis and Optimization,” Proc. European Design Automation Conf., Oct. 1992, pp. 328–333.
I. Ghosh, A. Raghunathan, and N.K. Jha, “Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs,” Proc. Design Automation Conf., June 1997, pp. 534–539.
S. Bhattacharya, S. Dey, and F. Brglez, “Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications,” Proc. Design Automation Conf., June 1994, pp. 491–496.
T. Niermann and J.H. Patel, “HITEC: A Test Generation Package for Sequential Circuits,” Proc. European Design Automation Conf., Feb. 1991, pp. 214–218.
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Ravi, S., Ghosh, I., Roy, R.K. et al. Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits. Journal of Electronic Testing 13, 201–212 (1998). https://doi.org/10.1023/A:1008314022796
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DOI: https://doi.org/10.1023/A:1008314022796